Implementation of a Wang algorithm based ATPG for combinational logic circuits
AuthorCunning, Steven J., 1963-
AdvisorHill, Fredrick J.
MetadataShow full item record
PublisherThe University of Arizona.
RightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
AbstractAutomatic Test Pattern Generation (ATPG) is the process of generating tests vectors for a circuit given only the physical description of that circuit. Many of today's ATPG systems are based on the D-Algorithm, PODEM, or FAN. This research is focused on the development and use of a more time efficient ATPG system for combinational logic circuits. The ATPG system developed by this research will be based on the Wang algorithm which uses a 9-value calculus. The fault model used is the single stuck-at fault model. Two versions of the system will be developed. The batch version will attempt to determine tests for all single stuck-at faults in the given circuit. The interactive version will allow the operator to select a single fault to be tested. The system will be written in C and developed for the MS-DOS microcomputer environment.