Persistent Link:
http://hdl.handle.net/10150/615766
Title:
QUATERNARY SHIFT REGISTER AND ITS APPLICATION TO DIGITAL SIGNAL PROCESSING
Author:
Zhou, R.; Mavretic, A.
Affiliation:
Boston University College of Engineering
Issue Date:
1985-10
Rights:
Copyright © International Foundation for Telemetering
Collection Information:
Proceedings from the International Telemetering Conference are made available by the International Foundation for Telemetering and the University of Arizona Libraries. Visit http://www.telemetry.org/index.php/contact-us if you have questions about items in this collection.
Publisher:
International Foundation for Telemetering
Journal:
International Telemetering Conference Proceedings
Abstract:
This paper will describe the design of a quaternary memory cell and a quaternary shift register. The concept used here is based on multiple-valued logic algebra, which can be extended to a design of other high radix memory cells and high radix shift registers. A comparison of the quaternary memory cell and quaternary shift register with its binary counterpart will be discussed. The reduction of device counts and interconnections in quaternary systems promisses a good future in digital signal processing and communication network design realized by VLSI technology.
Sponsors:
International Foundation for Telemetering
ISSN:
0884-5123; 0074-9079
Additional Links:
http://www.telemetry.org/

Full metadata record

DC FieldValue Language
dc.language.isoen_USen
dc.titleQUATERNARY SHIFT REGISTER AND ITS APPLICATION TO DIGITAL SIGNAL PROCESSINGen_US
dc.contributor.authorZhou, R.en
dc.contributor.authorMavretic, A.en
dc.contributor.departmentBoston University College of Engineeringen
dc.date.issued1985-10-
dc.rightsCopyright © International Foundation for Telemeteringen
dc.description.collectioninformationProceedings from the International Telemetering Conference are made available by the International Foundation for Telemetering and the University of Arizona Libraries. Visit http://www.telemetry.org/index.php/contact-us if you have questions about items in this collection.en
dc.publisherInternational Foundation for Telemeteringen
dc.description.abstractThis paper will describe the design of a quaternary memory cell and a quaternary shift register. The concept used here is based on multiple-valued logic algebra, which can be extended to a design of other high radix memory cells and high radix shift registers. A comparison of the quaternary memory cell and quaternary shift register with its binary counterpart will be discussed. The reduction of device counts and interconnections in quaternary systems promisses a good future in digital signal processing and communication network design realized by VLSI technology.en
dc.description.sponsorshipInternational Foundation for Telemeteringen
dc.identifier.issn0884-5123-
dc.identifier.issn0074-9079-
dc.identifier.urihttp://hdl.handle.net/10150/615766-
dc.identifier.journalInternational Telemetering Conference Proceedingsen
dc.typetexten
dc.typeProceedingsen
dc.relation.urlhttp://www.telemetry.org/en
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