Persistent Link:
http://hdl.handle.net/10150/614628
Title:
Single Board Bit Synchronizer
Author:
Burgess, George; Bridges, Lloyd
Affiliation:
Stanford Telecommunications, Inc.
Issue Date:
1989-11
Rights:
Copyright © International Foundation for Telemetering
Collection Information:
Proceedings from the International Telemetering Conference are made available by the International Foundation for Telemetering and the University of Arizona Libraries. Visit http://www.telemetry.org/index.php/contact-us if you have questions about items in this collection.
Publisher:
International Foundation for Telemetering
Journal:
International Telemetering Conference Proceedings
Abstract:
ASIC developments have made it possible to include the essential signal processing functions for data detection, clock recovery, and NCO in a single custom-designed chip. Using this chip and PLDs enabled the implementation of a fully-featured bit synchronizer on a single VME board in a rack-mountable 1.75" high, 19" wide chassis. This represents a space savings of 2/3 over existing units. The data rates supported are 250 bps to 5Mbps (2.5 Mbps biphase).
Sponsors:
International Foundation for Telemetering
ISSN:
0884-5123; 0074-9079
Additional Links:
http://www.telemetry.org/

Full metadata record

DC FieldValue Language
dc.language.isoen_USen
dc.titleSingle Board Bit Synchronizeren_US
dc.contributor.authorBurgess, Georgeen
dc.contributor.authorBridges, Lloyden
dc.contributor.departmentStanford Telecommunications, Inc.en
dc.date.issued1989-11-
dc.rightsCopyright © International Foundation for Telemeteringen
dc.description.collectioninformationProceedings from the International Telemetering Conference are made available by the International Foundation for Telemetering and the University of Arizona Libraries. Visit http://www.telemetry.org/index.php/contact-us if you have questions about items in this collection.en
dc.publisherInternational Foundation for Telemeteringen
dc.description.abstractASIC developments have made it possible to include the essential signal processing functions for data detection, clock recovery, and NCO in a single custom-designed chip. Using this chip and PLDs enabled the implementation of a fully-featured bit synchronizer on a single VME board in a rack-mountable 1.75" high, 19" wide chassis. This represents a space savings of 2/3 over existing units. The data rates supported are 250 bps to 5Mbps (2.5 Mbps biphase).en
dc.description.sponsorshipInternational Foundation for Telemeteringen
dc.identifier.issn0884-5123-
dc.identifier.issn0074-9079-
dc.identifier.urihttp://hdl.handle.net/10150/614628-
dc.identifier.journalInternational Telemetering Conference Proceedingsen
dc.typetexten
dc.typeProceedingsen
dc.relation.urlhttp://www.telemetry.org/en
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