LOW-POWER FAULT-TOLERANT MICROPROCESSOR-BASED DISTRIBUTED ARCHITECTURE FOR ON-BOARD SIGNAL PROCESSING

Persistent Link:
http://hdl.handle.net/10150/612436
Title:
LOW-POWER FAULT-TOLERANT MICROPROCESSOR-BASED DISTRIBUTED ARCHITECTURE FOR ON-BOARD SIGNAL PROCESSING
Author:
Haas, W. H.; Liao, H. H.; Schoknecht, W. E.
Affiliation:
Rockwell International
Issue Date:
1983-10
Rights:
Copyright © International Foundation for Telemetering
Collection Information:
Proceedings from the International Telemetering Conference are made available by the International Foundation for Telemetering and the University of Arizona Libraries. Visit http://www.telemetry.org/index.php/contact-us if you have questions about items in this collection.
Publisher:
International Foundation for Telemetering
Journal:
International Telemetering Conference Proceedings
Abstract:
Numerous future space-based systems are being conceived that will require the on-board processing of a volume of data many orders of magnitude greater than the current state-ofthe- art. Such systems must in addition be extremely low power and autonomously fault recoverable. This paper describes a microprocessor-based distributed architecture that has been evolving as a solution to this problem. This proposed architecture features three subarchitectures: synchronous pipeline, dedicated-channel microprocessor array, and multiplebus oriented microcomputer array; as well as internal data compression, distributed control and self testing, and a building block approach to system implementation. Emphasized is the roll of microprocessors in this architecture and the challenge of reducing the overhead required by fault-tolerant processing.
Sponsors:
International Foundation for Telemetering
ISSN:
0884-5123; 0074-9079
Additional Links:
http://www.telemetry.org/

Full metadata record

DC FieldValue Language
dc.language.isoen_USen
dc.titleLOW-POWER FAULT-TOLERANT MICROPROCESSOR-BASED DISTRIBUTED ARCHITECTURE FOR ON-BOARD SIGNAL PROCESSINGen_US
dc.contributor.authorHaas, W. H.en
dc.contributor.authorLiao, H. H.en
dc.contributor.authorSchoknecht, W. E.en
dc.contributor.departmentRockwell Internationalen
dc.date.issued1983-10-
dc.rightsCopyright © International Foundation for Telemeteringen
dc.description.collectioninformationProceedings from the International Telemetering Conference are made available by the International Foundation for Telemetering and the University of Arizona Libraries. Visit http://www.telemetry.org/index.php/contact-us if you have questions about items in this collection.en
dc.publisherInternational Foundation for Telemeteringen
dc.description.abstractNumerous future space-based systems are being conceived that will require the on-board processing of a volume of data many orders of magnitude greater than the current state-ofthe- art. Such systems must in addition be extremely low power and autonomously fault recoverable. This paper describes a microprocessor-based distributed architecture that has been evolving as a solution to this problem. This proposed architecture features three subarchitectures: synchronous pipeline, dedicated-channel microprocessor array, and multiplebus oriented microcomputer array; as well as internal data compression, distributed control and self testing, and a building block approach to system implementation. Emphasized is the roll of microprocessors in this architecture and the challenge of reducing the overhead required by fault-tolerant processing.en
dc.description.sponsorshipInternational Foundation for Telemeteringen
dc.identifier.issn0884-5123-
dc.identifier.issn0074-9079-
dc.identifier.urihttp://hdl.handle.net/10150/612436-
dc.identifier.journalInternational Telemetering Conference Proceedingsen
dc.typetexten
dc.typeProceedingsen
dc.relation.urlhttp://www.telemetry.org/en
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