Persistent Link:
http://hdl.handle.net/10150/611415
Title:
300 MBPS CCSDS Processing Using FPGA's
Author:
Genrich, Thad J.
Issue Date:
1996-10
Rights:
Copyright © International Foundation for Telemetering
Collection Information:
Proceedings from the International Telemetering Conference are made available by the International Foundation for Telemetering and the University of Arizona Libraries. Visit http://www.telemetry.org/index.php/contact-us if you have questions about items in this collection.
Publisher:
International Foundation for Telemetering
Journal:
International Telemetering Conference Proceedings
Abstract:
This paper describes a 300 Mega Bit Per Second (MBPS) Front End Processor (FEP) prototype completed in early 1993. The FEP implements a patent pending parallel frame synchronizer (frame sync) design in 12 Actel 1240 Field Programmable Gate Arrays (FPGA's). The FEP also provides (255,223) Reed-Solomon (RS) decoding and a High Performance Parallel Interface (HIPPI) output interface. The recent introduction of large RAM based FPGA's allows greater high speed data processing integration and flexibility to be achieved. A proposed FEP implementation based on Altera 10K50 FPGA's is described. This design can be implemented on a single slot 6U VME module, and includes a PCI Mezzanine Card (PMC) for a commercial Fibre Channel or Asynchronous Transfer Mode (ATM) output interface module. Concepts for implementation of (255,223) RS and Landsat 7 Bose-Chaudhuri-Hocquenghem (BCH) decoding in FPGA's are also presented. The paper concludes with a summary of the advantages of high speed data processing in FPGA's over Application Specific Integrated Circuit (ASIC) based approaches. Other potential data processing applications are also discussed.
Keywords:
CCSDS Telemetry Processing; High Speed Frame Synchronization; Reed-Solomon (RS) Decoding; BCH Decoding; Rice Decompression; Field Programmable Gate Array (FPGA); VME; FUSIONTM; Fibre Channel; Asynchronous Transfer Mode (ATM); RACEway; PCI Mezzanine Card (PMC); RS Error Correction Chip (RSEC); Landsat 7 BCH Decoder
Sponsors:
International Foundation for Telemetering
ISSN:
0884-5123; 0074-9079
Additional Links:
http://www.telemetry.org/

Full metadata record

DC FieldValue Language
dc.language.isoen_USen
dc.title300 MBPS CCSDS Processing Using FPGA'sen_US
dc.contributor.authorGenrich, Thad J.en
dc.date.issued1996-10-
dc.rightsCopyright © International Foundation for Telemeteringen
dc.description.collectioninformationProceedings from the International Telemetering Conference are made available by the International Foundation for Telemetering and the University of Arizona Libraries. Visit http://www.telemetry.org/index.php/contact-us if you have questions about items in this collection.en
dc.publisherInternational Foundation for Telemeteringen
dc.description.abstractThis paper describes a 300 Mega Bit Per Second (MBPS) Front End Processor (FEP) prototype completed in early 1993. The FEP implements a patent pending parallel frame synchronizer (frame sync) design in 12 Actel 1240 Field Programmable Gate Arrays (FPGA's). The FEP also provides (255,223) Reed-Solomon (RS) decoding and a High Performance Parallel Interface (HIPPI) output interface. The recent introduction of large RAM based FPGA's allows greater high speed data processing integration and flexibility to be achieved. A proposed FEP implementation based on Altera 10K50 FPGA's is described. This design can be implemented on a single slot 6U VME module, and includes a PCI Mezzanine Card (PMC) for a commercial Fibre Channel or Asynchronous Transfer Mode (ATM) output interface module. Concepts for implementation of (255,223) RS and Landsat 7 Bose-Chaudhuri-Hocquenghem (BCH) decoding in FPGA's are also presented. The paper concludes with a summary of the advantages of high speed data processing in FPGA's over Application Specific Integrated Circuit (ASIC) based approaches. Other potential data processing applications are also discussed.en
dc.subjectCCSDS Telemetry Processingen
dc.subjectHigh Speed Frame Synchronizationen
dc.subjectReed-Solomon (RS) Decodingen
dc.subjectBCH Decodingen
dc.subjectRice Decompressionen
dc.subjectField Programmable Gate Array (FPGA)en
dc.subjectVMEen
dc.subjectFUSIONTMen
dc.subjectFibre Channelen
dc.subjectAsynchronous Transfer Mode (ATM)en
dc.subjectRACEwayen
dc.subjectPCI Mezzanine Card (PMC)en
dc.subjectRS Error Correction Chip (RSEC)en
dc.subjectLandsat 7 BCH Decoderen
dc.description.sponsorshipInternational Foundation for Telemeteringen
dc.identifier.issn0884-5123-
dc.identifier.issn0074-9079-
dc.identifier.urihttp://hdl.handle.net/10150/611415-
dc.identifier.journalInternational Telemetering Conference Proceedingsen
dc.typetexten
dc.typeProceedingsen
dc.relation.urlhttp://www.telemetry.org/en
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