Persistent Link:
http://hdl.handle.net/10150/306095
Title:
Passivation of III-V Semiconductor Surfaces
Author:
Contreras, Yissel; Muscat, Anthony
Affiliation:
Department of Chemical and Environmental Engineering, University of Arizona; Department of Chemical and Environmental Engineering, University of Arizona
Issue Date:
2013-11-08
Rights:
Copyright © is held by the author.
Collection Information:
This item is part of the GPSC Student Showcase collection. For more information about the Student Showcase, please email the GPSC (Graduate and Professional Student Council) at gpsc@email.arizona.edu.
Abstract:
Computer processor chips of the last generation are based on silicon, modified to achieve maximum charge mobility to enable fast switching speeds at low power. III-V semiconductors have charge mobilities that are much higher than that of silicon making them suitable candidates for boosting the performance of new electronic devices. However, III-V semiconductors oxidize rapidly in air after oxide etching and the poor quality of the resulting oxide limits device performance. Our goal is to design a liquid-phase process flow to etch the oxide and passivate the surface of III-V semiconductors and to understand the mechanism of layer formation.Self-assembled monolayers of 1-eicosanethiol (ET) dissolved in ethanol, IPA, chloroform, and toluene were deposited on clean InSb(100) surfaces. The InSb passivated surfaces were characterized after 0 to 60 min of exposure to air. Ellipsometry measurements showed a starting overlayer thickness (due to ET, oxides, or both) of about 20 Å in chloroform and from 32 to 35 Å in alcohols and toluene. Surface composition analysis of InSb with X-ray photoelectron spectroscopy after passivation with 0.1 mM ET in ethanol confirmed the presence of ET and showed that oxygen in the Auger region is below detection limits up to 3 min after the passivation. Our results show that a thiol layer on top of a non-oxidized or low-oxide semiconductor surface slows oxygen diffusion in comparison to a surface with no thiol present, making this a promising passivation method of III-V semiconductors.
Keywords:
III-V semiconductors; passivation; self-assembled monolayers; XPS
Sponsors:
Intel Corporation, National Council of Science and Technology (CONACYT, México)

Full metadata record

DC FieldValue Language
dc.contributor.authorContreras, Yisselen_US
dc.contributor.authorMuscat, Anthonyen_US
dc.date.accessioned2013-12-02T17:47:51Z-
dc.date.available2013-12-02T17:47:51Z-
dc.date.issued2013-11-08-
dc.identifier.urihttp://hdl.handle.net/10150/306095-
dc.description.abstractComputer processor chips of the last generation are based on silicon, modified to achieve maximum charge mobility to enable fast switching speeds at low power. III-V semiconductors have charge mobilities that are much higher than that of silicon making them suitable candidates for boosting the performance of new electronic devices. However, III-V semiconductors oxidize rapidly in air after oxide etching and the poor quality of the resulting oxide limits device performance. Our goal is to design a liquid-phase process flow to etch the oxide and passivate the surface of III-V semiconductors and to understand the mechanism of layer formation.Self-assembled monolayers of 1-eicosanethiol (ET) dissolved in ethanol, IPA, chloroform, and toluene were deposited on clean InSb(100) surfaces. The InSb passivated surfaces were characterized after 0 to 60 min of exposure to air. Ellipsometry measurements showed a starting overlayer thickness (due to ET, oxides, or both) of about 20 Å in chloroform and from 32 to 35 Å in alcohols and toluene. Surface composition analysis of InSb with X-ray photoelectron spectroscopy after passivation with 0.1 mM ET in ethanol confirmed the presence of ET and showed that oxygen in the Auger region is below detection limits up to 3 min after the passivation. Our results show that a thiol layer on top of a non-oxidized or low-oxide semiconductor surface slows oxygen diffusion in comparison to a surface with no thiol present, making this a promising passivation method of III-V semiconductors.en_US
dc.description.sponsorshipIntel Corporation, National Council of Science and Technology (CONACYT, México)en_US
dc.language.isoen_USen_US
dc.rightsCopyright © is held by the author.en_US
dc.subjectIII-V semiconductorsen_US
dc.subjectpassivationen_US
dc.subjectself-assembled monolayersen_US
dc.subjectXPSen_US
dc.titlePassivation of III-V Semiconductor Surfacesen_US
dc.contributor.departmentDepartment of Chemical and Environmental Engineering, University of Arizonaen_US
dc.contributor.departmentDepartment of Chemical and Environmental Engineering, University of Arizonaen_US
dc.description.collectioninformationThis item is part of the GPSC Student Showcase collection. For more information about the Student Showcase, please email the GPSC (Graduate and Professional Student Council) at gpsc@email.arizona.edu.en_US
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