Persistent Link:
http://hdl.handle.net/10150/292048
Title:
Circuit emulation in a packet switching network
Author:
Nagulpally, Durga Mahalaxmi, 1965-
Issue Date:
1992
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
When continuous bit streams are transmitted over packet switching networks, the 'packetized' version of the real time traffic in a periodic sequence is distorted due to random transmission delay and packet loss. The need to recover the original continuous bit stream requires an estimation of the original source clock. This clock regeneration is called Circuit Emulation. Using a single phase lock loop is insufficient since the packet arrival jitter (PAJ) is generally very large. A circuit emulation technique that has been recently proposed provides algorithms to estimate the frequency difference between the original transmitter clock and a local retiming clock. A tracking loop similar to a PLL has been designed in this thesis to regenerate the original transmitter clock from the frequency difference estimated. Performance and simulation are studied for the PLL. It is found that by an appropriate choice of the tracking loop parameters, the transmitter clock can be regenerated with minimal jitter and delay.
Type:
text; Thesis-Reproduction (electronic)
Keywords:
Engineering, Electronics and Electrical.
Degree Name:
M.S.
Degree Level:
masters
Degree Program:
Graduate College; Electrical and Computer Engineering
Degree Grantor:
University of Arizona
Advisor:
Liu, Ming-Kang

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleCircuit emulation in a packet switching networken_US
dc.creatorNagulpally, Durga Mahalaxmi, 1965-en_US
dc.contributor.authorNagulpally, Durga Mahalaxmi, 1965-en_US
dc.date.issued1992en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractWhen continuous bit streams are transmitted over packet switching networks, the 'packetized' version of the real time traffic in a periodic sequence is distorted due to random transmission delay and packet loss. The need to recover the original continuous bit stream requires an estimation of the original source clock. This clock regeneration is called Circuit Emulation. Using a single phase lock loop is insufficient since the packet arrival jitter (PAJ) is generally very large. A circuit emulation technique that has been recently proposed provides algorithms to estimate the frequency difference between the original transmitter clock and a local retiming clock. A tracking loop similar to a PLL has been designed in this thesis to regenerate the original transmitter clock from the frequency difference estimated. Performance and simulation are studied for the PLL. It is found that by an appropriate choice of the tracking loop parameters, the transmitter clock can be regenerated with minimal jitter and delay.en_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.subjectEngineering, Electronics and Electrical.en_US
thesis.degree.nameM.S.en_US
thesis.degree.levelmastersen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorLiu, Ming-Kangen_US
dc.identifier.proquest1350794en_US
dc.identifier.bibrecord.b25469903en_US
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