Persistent Link:
http://hdl.handle.net/10150/292038
Title:
HPSIM4A: Simulating multiple clocks and functional registers
Author:
Brown, Joseph Nagy, 1959-
Issue Date:
1989
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
Universal AHPL, a hardware description language, is supported by a function level simulator. Driving the simulation is a data base, generated by STAGE1 of the Three-Stage Hardware Compiler, and the output of the COMSEC Processor, which provides the user with control over the simulation and the printed results. This paper describes the design and use of the function level simulator HPSIM4A, a refined extension of its predecessor, HPSIM4. HPSIM4A is a thoroughly tested and debugged version of HPSIM4 with additional features that utilize more of Universal AHPL's descriptive capabilities. In particular, the multiple clock, the specific driving clock and the User-Defined Functional Register capabilities can now be simulated. Additionally, provision has been made to simulate both positive and negative edge triggered flip-flops and User-Defined Combinational Logic Units with a minimal programming effort.
Type:
text; Thesis-Reproduction (electronic)
Keywords:
Computer engineering.; Integrated circuits -- Computer simulation.
Degree Name:
M.S.
Degree Level:
masters
Degree Program:
Graduate College; Electrical and Computer Engineering
Degree Grantor:
University of Arizona
Advisor:
Hill, Fredrick J.

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleHPSIM4A: Simulating multiple clocks and functional registersen_US
dc.creatorBrown, Joseph Nagy, 1959-en_US
dc.contributor.authorBrown, Joseph Nagy, 1959-en_US
dc.date.issued1989en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractUniversal AHPL, a hardware description language, is supported by a function level simulator. Driving the simulation is a data base, generated by STAGE1 of the Three-Stage Hardware Compiler, and the output of the COMSEC Processor, which provides the user with control over the simulation and the printed results. This paper describes the design and use of the function level simulator HPSIM4A, a refined extension of its predecessor, HPSIM4. HPSIM4A is a thoroughly tested and debugged version of HPSIM4 with additional features that utilize more of Universal AHPL's descriptive capabilities. In particular, the multiple clock, the specific driving clock and the User-Defined Functional Register capabilities can now be simulated. Additionally, provision has been made to simulate both positive and negative edge triggered flip-flops and User-Defined Combinational Logic Units with a minimal programming effort.en_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.subjectComputer engineering.en_US
dc.subjectIntegrated circuits -- Computer simulation.en_US
thesis.degree.nameM.S.en_US
thesis.degree.levelmastersen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorHill, Fredrick J.en_US
dc.identifier.proquest1336544en_US
dc.identifier.oclc22852930en_US
dc.identifier.bibrecord.b17510600en_US
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