YOR: A yield optimizing routing algorithm by minimizing critical areas and vias

Persistent Link:
http://hdl.handle.net/10150/292026
Title:
YOR: A yield optimizing routing algorithm by minimizing critical areas and vias
Author:
Chang, Ting-Mao, 1962-
Issue Date:
1991
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
Traditionally, the goal of channel routing algorithms is to route the nets with as few tracks as possible to minimize the chip area and achieve 100 percent connection. However, the manufacturing yield may not reach a satisfactory level if care is not taken to reduce the critical areas which are susceptible to defects. Our approach is to systematically eliminate critical areas by floating, burying, and bumping net segments as well as shifting vias. The yield optimizing routing (YOR) algorithm also minimizes the number of vias since vias in a chip increase the manufacturing complexity which again degrades the yield. The algorithm has been implemented and applied to benchmark routing layouts in the literature. The experimental results show that large reduction in the number of critical areas and significant improvement in yield are achieved, particularly for practical size channels such as the Deutsch's difficult problem.
Type:
text; Thesis-Reproduction (electronic)
Keywords:
Engineering, Electronics and Electrical.
Degree Name:
M.S.
Degree Level:
masters
Degree Program:
Graduate College; Electrical and Computer Engineering
Degree Grantor:
University of Arizona
Advisor:
Kuo, Sy-Yen

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleYOR: A yield optimizing routing algorithm by minimizing critical areas and viasen_US
dc.creatorChang, Ting-Mao, 1962-en_US
dc.contributor.authorChang, Ting-Mao, 1962-en_US
dc.date.issued1991en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractTraditionally, the goal of channel routing algorithms is to route the nets with as few tracks as possible to minimize the chip area and achieve 100 percent connection. However, the manufacturing yield may not reach a satisfactory level if care is not taken to reduce the critical areas which are susceptible to defects. Our approach is to systematically eliminate critical areas by floating, burying, and bumping net segments as well as shifting vias. The yield optimizing routing (YOR) algorithm also minimizes the number of vias since vias in a chip increase the manufacturing complexity which again degrades the yield. The algorithm has been implemented and applied to benchmark routing layouts in the literature. The experimental results show that large reduction in the number of critical areas and significant improvement in yield are achieved, particularly for practical size channels such as the Deutsch's difficult problem.en_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.subjectEngineering, Electronics and Electrical.en_US
thesis.degree.nameM.S.en_US
thesis.degree.levelmastersen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorKuo, Sy-Yenen_US
dc.identifier.proquest1343414en_US
dc.identifier.bibrecord.b2672778xen_US
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