Persistent Link:
http://hdl.handle.net/10150/291633
Title:
Delay timing of Sea-of-Wire Array Logic
Author:
Wang, Michael Chih-Huei, 1967-
Issue Date:
1993
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
Sea-of-Wire Array Logic has been developed to support a symbolic layout algorithm realization. A delay timing scheme is needed to direct the placement strategy of the layout. Both SPICE simulation and table lookup method are compared to verify the accuracy of delay estimation. Input waveform distortion is taken into account in the timing analysis, and correction factors are applied to increase the accuracy of delay estimation. A table lookup scheme has shown to be very accurate in comparison with SPICE value. A set of benchmark circuits have been applied to evaluate this table lookup scheme. The results obtained demonstrate a greater than 90% accuracy and five orders of magnitude increase in speed over SPICE simulation.
Type:
text; Thesis-Reproduction (electronic)
Keywords:
Engineering, Electronics and Electrical.
Degree Name:
M.S.
Degree Level:
masters
Degree Program:
Graduate College; Electrical and Computer Engineeering
Degree Grantor:
University of Arizona
Advisor:
Hill, Frederick J.

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleDelay timing of Sea-of-Wire Array Logicen_US
dc.creatorWang, Michael Chih-Huei, 1967-en_US
dc.contributor.authorWang, Michael Chih-Huei, 1967-en_US
dc.date.issued1993en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractSea-of-Wire Array Logic has been developed to support a symbolic layout algorithm realization. A delay timing scheme is needed to direct the placement strategy of the layout. Both SPICE simulation and table lookup method are compared to verify the accuracy of delay estimation. Input waveform distortion is taken into account in the timing analysis, and correction factors are applied to increase the accuracy of delay estimation. A table lookup scheme has shown to be very accurate in comparison with SPICE value. A set of benchmark circuits have been applied to evaluate this table lookup scheme. The results obtained demonstrate a greater than 90% accuracy and five orders of magnitude increase in speed over SPICE simulation.en_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.subjectEngineering, Electronics and Electrical.en_US
thesis.degree.nameM.S.en_US
thesis.degree.levelmastersen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeeringen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorHill, Frederick J.en_US
dc.identifier.proquest1352328en_US
dc.identifier.bibrecord.b27085855en_US
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