Persistent Link:
http://hdl.handle.net/10150/291500
Title:
A hardware compiler for VLSI synthesis applications
Author:
Chen, Jianxin, 1963-
Issue Date:
1992
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
Hardware description languages have been playing key roles in today's VLSI synthesis systems. AHPL is a hardware description language that can simplify the VLSI circuit design. An AHPL based VLSI synthesis system is introduced. HPCOM, a hardware compiler that translates an AHPL description into a logic network is a major part of the system. My research focuses on the development, use and interfacing between HPCOM and other synthesis tools. A finite state machine design that maps to the AHPL structure with minimal memory elements is developed. A minimization tool is incorporated into the HPCOM for Boolean logic minimization. Bus sub-type, an application-dependent parameter, and user defined logic are implemented. Memory contention problems are solved using overlay linking technique. Data structures of the HPCOM and methods for improving the usage of storage are discussed. A completed description of the data base produced by the compiler is provided.
Type:
text; Thesis-Reproduction (electronic)
Keywords:
Engineering, Electronics and Electrical.
Degree Name:
M.S.
Degree Level:
masters
Degree Program:
Graduate College; Electrical and Computer Engineering
Degree Grantor:
University of Arizona
Advisor:
Hill, Fredrick J.

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleA hardware compiler for VLSI synthesis applicationsen_US
dc.creatorChen, Jianxin, 1963-en_US
dc.contributor.authorChen, Jianxin, 1963-en_US
dc.date.issued1992en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractHardware description languages have been playing key roles in today's VLSI synthesis systems. AHPL is a hardware description language that can simplify the VLSI circuit design. An AHPL based VLSI synthesis system is introduced. HPCOM, a hardware compiler that translates an AHPL description into a logic network is a major part of the system. My research focuses on the development, use and interfacing between HPCOM and other synthesis tools. A finite state machine design that maps to the AHPL structure with minimal memory elements is developed. A minimization tool is incorporated into the HPCOM for Boolean logic minimization. Bus sub-type, an application-dependent parameter, and user defined logic are implemented. Memory contention problems are solved using overlay linking technique. Data structures of the HPCOM and methods for improving the usage of storage are discussed. A completed description of the data base produced by the compiler is provided.en_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.subjectEngineering, Electronics and Electrical.en_US
thesis.degree.nameM.S.en_US
thesis.degree.levelmastersen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorHill, Fredrick J.en_US
dc.identifier.proquest1350935en_US
dc.identifier.bibrecord.b26422700en_US
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