Persistent Link:
http://hdl.handle.net/10150/291439
Title:
A package efficient PC based AHPL to EDIF translator
Author:
Lim, Yeow Lam, 1962-
Issue Date:
1990
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
Computed-Aided Design tools have assisted the digital designer at various levels of the design process. AHPL, A Hardware Programming Language, is a hardware description language which allows a digital system to be described at the register transfer level. AHPL circuit descriptions can be translated into logic gate networks using the HPCOM hardware compiler. The Electronic Design Interchange Format (EDIF) is a data exchange standard used to exchange data between CAD tools. By providing a translator to convert the logic gate networks from HPCOM into EDIF Netlist format, designs described in AHPL can be ported to other CAD tools. This thesis documents the development and implementation of a EDIF Netlist translator for the HPCOM generated logic network. The translator is designed to use every gate in a package and includes an option that converts logic gates to their NAND equivalents. Netlist outputs from the translator are simulated with the OrCAD Verification and Simulation Tools. These simulations are then compared with simulations from HPSIM to make sure the netlist output from the translator is indeed a gate level representation of the design as described by AHPL.
Type:
text; Thesis-Reproduction (electronic)
Keywords:
Engineering, Electronics and Electrical.
Degree Name:
M.S.
Degree Level:
masters
Degree Program:
Graduate College; Electrical and Computer Engineering
Degree Grantor:
University of Arizona
Advisor:
Hill, Fredrick J.

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleA package efficient PC based AHPL to EDIF translatoren_US
dc.creatorLim, Yeow Lam, 1962-en_US
dc.contributor.authorLim, Yeow Lam, 1962-en_US
dc.date.issued1990en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractComputed-Aided Design tools have assisted the digital designer at various levels of the design process. AHPL, A Hardware Programming Language, is a hardware description language which allows a digital system to be described at the register transfer level. AHPL circuit descriptions can be translated into logic gate networks using the HPCOM hardware compiler. The Electronic Design Interchange Format (EDIF) is a data exchange standard used to exchange data between CAD tools. By providing a translator to convert the logic gate networks from HPCOM into EDIF Netlist format, designs described in AHPL can be ported to other CAD tools. This thesis documents the development and implementation of a EDIF Netlist translator for the HPCOM generated logic network. The translator is designed to use every gate in a package and includes an option that converts logic gates to their NAND equivalents. Netlist outputs from the translator are simulated with the OrCAD Verification and Simulation Tools. These simulations are then compared with simulations from HPSIM to make sure the netlist output from the translator is indeed a gate level representation of the design as described by AHPL.en_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.subjectEngineering, Electronics and Electrical.en_US
thesis.degree.nameM.S.en_US
thesis.degree.levelmastersen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorHill, Fredrick J.en_US
dc.identifier.proquest1339888en_US
dc.identifier.bibrecord.b2622222xen_US
All Items in UA Campus Repository are protected by copyright, with all rights reserved, unless otherwise indicated.