An asynchronous, single-chip, LMS based, adaptive fir echo canceller

Persistent Link:
http://hdl.handle.net/10150/291387
Title:
An asynchronous, single-chip, LMS based, adaptive fir echo canceller
Author:
Mackey, Richard Paul
Issue Date:
1995
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
An asynchronous, single-chip, high-speed communication adaptive echo canceller was developed during this research. Adaptation is based on the LMS algorithm with power-of-two convergence factor. Cancellation is performed by a 128-coefficient adaptive finite impulse response filter whose coefficients are updated every cycle. The LMS power-of-two update equations were modified to allow a pipelined implementation. Pipelining the adaptation and echo estimation operations enabled hardware minimization, a high sampling rate, and no increase in convergence time. The resulting circuit updates the filter coefficients and generates the output at a sampling rate greater than 205 kHz. The chip was designed using 0.8 mum CMOS standard cells. The single-chip layout requires a die size of 9.25 mm by 7.25 mm.
Type:
text; Thesis-Reproduction (electronic)
Keywords:
Engineering, Electronics and Electrical.; Computer Science.
Degree Name:
M.S.
Degree Level:
masters
Degree Program:
Graduate College; Electrical and Computer Engineering
Degree Grantor:
University of Arizona
Advisor:
Rodriguez, Jeffrey J.

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleAn asynchronous, single-chip, LMS based, adaptive fir echo cancelleren_US
dc.creatorMackey, Richard Paulen_US
dc.contributor.authorMackey, Richard Paulen_US
dc.date.issued1995en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractAn asynchronous, single-chip, high-speed communication adaptive echo canceller was developed during this research. Adaptation is based on the LMS algorithm with power-of-two convergence factor. Cancellation is performed by a 128-coefficient adaptive finite impulse response filter whose coefficients are updated every cycle. The LMS power-of-two update equations were modified to allow a pipelined implementation. Pipelining the adaptation and echo estimation operations enabled hardware minimization, a high sampling rate, and no increase in convergence time. The resulting circuit updates the filter coefficients and generates the output at a sampling rate greater than 205 kHz. The chip was designed using 0.8 mum CMOS standard cells. The single-chip layout requires a die size of 9.25 mm by 7.25 mm.en_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.subjectEngineering, Electronics and Electrical.en_US
dc.subjectComputer Science.en_US
thesis.degree.nameM.S.en_US
thesis.degree.levelmastersen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorRodriguez, Jeffrey J.en_US
dc.identifier.proquest1362221en_US
dc.identifier.bibrecord.b3331102x9en_US
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