Persistent Link:
http://hdl.handle.net/10150/289066
Title:
The effect of copper contamination on thin gate oxide integrity
Author:
Vermeire, Bert Marcel
Issue Date:
1999
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
Contamination of silicon with trace amounts of copper during processing can adversely affect the gate oxide integrity of integrated circuits, resulting in substantial yield loss and reliability problems. Because of increased use of copper as interconnect material, cross-contamination during the production process must be avoided. Establishing adequate protocols for wafer handling and tool use requires understanding of the mechanisms by which copper affects the gate oxide and knowledge of acceptable contamination limits. The effect of copper contamination on thin gate oxide integrity was studied by purposely introducing small amounts of copper in controlled contamination experiments. Copper contamination causes gate oxide defects by precipitating near the Si/SiO₂ interface when the silicon is cooled from the processing temperature. The concentration at which defects start to appear on flat capacitors decreases with decreasing oxide thickness. When copper contamination from a contaminated ammonium hydroxide peroxide mixture cleaning solution occurs, deposition of more than 7 x 10¹⁰ atoms/cm² is required before the gate oxide integrity of 3 nm oxides is affected. Such levels are not readily exceeded in state of the art integrated circuit fabrication facilities using high-grade chemicals. Copper deposition from contaminated hydrofluoric acid (HF) solutions results in oxide lifetime degradation for 3 nm oxides even when less than 1 x 10¹⁰ atoms/cm² is deposited. The copper catalyzes hydrogen evolution, which in turn causes dissolution, and thus roughening, of the silicon surface. Roughening of the silicon is responsible for the reduced oxide quality. Thus, removal of the copper after contamination has occurred does not lead to recovery of the oxide quality. A copper contaminated silicon surface, which is immersed in uncontaminated HF, will also have reduced oxide lifetime. Precipitation occurs more readily at field overlap regions, since these regions have a large amount of mechanical stress, which getters contaminants and allows precipitates to nucleate and grow more easily. Field overlap precipitates result in a large field overlap-related defect density when copper contamination occurs. Copper contamination from contaminated HF also results in bumps in an oxide that is subsequently grown on the surface. These local regions of thicker oxide can lead to threshold voltage non-uniformity.
Type:
text; Dissertation-Reproduction (electronic)
Keywords:
Engineering, Electronics and Electrical.
Degree Name:
Ph.D.
Degree Level:
doctoral
Degree Program:
Graduate College; Electrical and Computer Engineering
Degree Grantor:
University of Arizona
Advisor:
Parks, Harold G.

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleThe effect of copper contamination on thin gate oxide integrityen_US
dc.creatorVermeire, Bert Marcelen_US
dc.contributor.authorVermeire, Bert Marcelen_US
dc.date.issued1999en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractContamination of silicon with trace amounts of copper during processing can adversely affect the gate oxide integrity of integrated circuits, resulting in substantial yield loss and reliability problems. Because of increased use of copper as interconnect material, cross-contamination during the production process must be avoided. Establishing adequate protocols for wafer handling and tool use requires understanding of the mechanisms by which copper affects the gate oxide and knowledge of acceptable contamination limits. The effect of copper contamination on thin gate oxide integrity was studied by purposely introducing small amounts of copper in controlled contamination experiments. Copper contamination causes gate oxide defects by precipitating near the Si/SiO₂ interface when the silicon is cooled from the processing temperature. The concentration at which defects start to appear on flat capacitors decreases with decreasing oxide thickness. When copper contamination from a contaminated ammonium hydroxide peroxide mixture cleaning solution occurs, deposition of more than 7 x 10¹⁰ atoms/cm² is required before the gate oxide integrity of 3 nm oxides is affected. Such levels are not readily exceeded in state of the art integrated circuit fabrication facilities using high-grade chemicals. Copper deposition from contaminated hydrofluoric acid (HF) solutions results in oxide lifetime degradation for 3 nm oxides even when less than 1 x 10¹⁰ atoms/cm² is deposited. The copper catalyzes hydrogen evolution, which in turn causes dissolution, and thus roughening, of the silicon surface. Roughening of the silicon is responsible for the reduced oxide quality. Thus, removal of the copper after contamination has occurred does not lead to recovery of the oxide quality. A copper contaminated silicon surface, which is immersed in uncontaminated HF, will also have reduced oxide lifetime. Precipitation occurs more readily at field overlap regions, since these regions have a large amount of mechanical stress, which getters contaminants and allows precipitates to nucleate and grow more easily. Field overlap precipitates result in a large field overlap-related defect density when copper contamination occurs. Copper contamination from contaminated HF also results in bumps in an oxide that is subsequently grown on the surface. These local regions of thicker oxide can lead to threshold voltage non-uniformity.en_US
dc.typetexten_US
dc.typeDissertation-Reproduction (electronic)en_US
dc.subjectEngineering, Electronics and Electrical.en_US
thesis.degree.namePh.D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorParks, Harold G.en_US
dc.identifier.proquest9960236en_US
dc.identifier.bibrecord.b40271754en_US
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