Persistent Link:
http://hdl.handle.net/10150/288924
Title:
Logic synthesis for low power
Author:
Wang, Qi
Issue Date:
1998
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
The dissertation addresses several problems in the power optimization and power-delay tradeoffs in digital CMOS circuits. The work is organized according to the three main sources of power dissipation: Power dissipation due to switching (P(sc)), standby or leakage power (P(leak)) and short circuit power (P(sc)). First we present new, efficient and provably correct algorithms for minimizing the switching power in combinational and sequential CMOS logic circuits. The techniques are based on the addition and removal of redundancies at the logic level. The basic technique developed for combinational circuits is extended to sequential circuits. Results of experiments carried on large (thousands of logic gates) commerical circuits (of the PowerPC chip) will be presented. Power dissipation due to the short circuit current has received much less attention. For submicron MOSFETs, this can be comparable to the switching power. A new, and computationally tractable model for the short circuit current in CMOS inverters and more complex CMOS gates was developed. This model was verified using a commerical 0.25 μm CMOS library and device models. The problem of minimizing the standby power for deep submicron technology is also addressed. The standby power dissipation has often been ignored in the design of CMOS circuits since its contribution to the total power dissipation has been negligable. However as device dimensions and voltages are scaled down, the standby power can be of the same order of magnitude as the switching power. This is a serious problem of many portable devices as they are in standby mode for considerable periods of time. One approach to alleviate this problem is the use of dual threshold voltages. We developed several new algorithms that optimally assign one of two threshold voltages to CMOS gates so as to minimize the standby power without sacrificing performance. The new algorithms handle circuits of thousands of gates and it is shown that the standby power can be reduced by as much as an order of magnitude without any loss of performance.
Type:
text; Dissertation-Reproduction (electronic)
Keywords:
Engineering, Electronics and Electrical.
Degree Name:
Ph.D.
Degree Level:
doctoral
Degree Program:
Graduate College; Electrical and Computer Engineering
Degree Grantor:
University of Arizona
Advisor:
Vrudhula, Sarma B. K.

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleLogic synthesis for low poweren_US
dc.creatorWang, Qien_US
dc.contributor.authorWang, Qien_US
dc.date.issued1998en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractThe dissertation addresses several problems in the power optimization and power-delay tradeoffs in digital CMOS circuits. The work is organized according to the three main sources of power dissipation: Power dissipation due to switching (P(sc)), standby or leakage power (P(leak)) and short circuit power (P(sc)). First we present new, efficient and provably correct algorithms for minimizing the switching power in combinational and sequential CMOS logic circuits. The techniques are based on the addition and removal of redundancies at the logic level. The basic technique developed for combinational circuits is extended to sequential circuits. Results of experiments carried on large (thousands of logic gates) commerical circuits (of the PowerPC chip) will be presented. Power dissipation due to the short circuit current has received much less attention. For submicron MOSFETs, this can be comparable to the switching power. A new, and computationally tractable model for the short circuit current in CMOS inverters and more complex CMOS gates was developed. This model was verified using a commerical 0.25 μm CMOS library and device models. The problem of minimizing the standby power for deep submicron technology is also addressed. The standby power dissipation has often been ignored in the design of CMOS circuits since its contribution to the total power dissipation has been negligable. However as device dimensions and voltages are scaled down, the standby power can be of the same order of magnitude as the switching power. This is a serious problem of many portable devices as they are in standby mode for considerable periods of time. One approach to alleviate this problem is the use of dual threshold voltages. We developed several new algorithms that optimally assign one of two threshold voltages to CMOS gates so as to minimize the standby power without sacrificing performance. The new algorithms handle circuits of thousands of gates and it is shown that the standby power can be reduced by as much as an order of magnitude without any loss of performance.en_US
dc.typetexten_US
dc.typeDissertation-Reproduction (electronic)en_US
dc.subjectEngineering, Electronics and Electrical.en_US
thesis.degree.namePh.D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorVrudhula, Sarma B. K.en_US
dc.identifier.proquest9912148en_US
dc.identifier.bibrecord.b39124770en_US
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