Concurrent substrate coupling noise modeling and active noise reduction methodology for mixed-signal physical design

Persistent Link:
http://hdl.handle.net/10150/284133
Title:
Concurrent substrate coupling noise modeling and active noise reduction methodology for mixed-signal physical design
Author:
Liu, Tingyang
Issue Date:
1999
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
In mixed-signal ICs that integrate complex digital circuits together with high-performance analog circuits, signal contamination caused by substrate coupling noise is a critical issue. Fast digital transients can produce noise harmful to the sensitive analog circuits. The noise can be coupled from noisy devices and interconnects into the common substrate and coupled into analog devices. This noise coupling mechanism poses serious challenges toward the signal integrity of the mixed-signal design. The final performance of the ICs signal integrity is heavily dependent on layout schemes and the effectiveness of using noise reduction techniques. A hierarchical substrate coupling noise modeling technique that uses a gate-level lumped parasitic circuit model (for digital circuit layout) and concurrent real-time stimulating waveforms has been developed. This hierarchical approach make the concurrent substrate coupling noise analysis feasible under the current computational resource limitation. The gate-level parasitic extraction can avoid the intensive computation needed by detailed source/drain level modeling technique while keeping a reasonable accuracy with respect to parasitics. The parasitic extraction is also a separate process from the substrate three-dimensional mesh generation process. Therefore, this modeling technique can be easily used for evaluation of different physical design schemes. An innovate active noise reduction method, using the noise cancellation mechanism during the physical design phase to reduce the substrate coupling noise contamination, has also been developed. The fundamental idea of this method is to use the reversely amplified noise to achieve a "virtual" ground for the substrate. The noise is sampled from the substrate and reversely amplified and then re-injected into the substrate, by this method, up to 90% of the original noise can be eliminated. The active substrate coupling noise reduction method has the merit that it can be used together with traditional noise reduction methods such as guard ring deployment. Several test chips have been designed and fabricated to demonstrate the effectiveness of the substrate modeling and reduction methods. In the results section of this dissertation, results from both SPICE-based simulation and measurement from MOSIS 1.2 micron test chips are presented and analyzed.
Type:
text; Dissertation-Reproduction (electronic)
Keywords:
Engineering, Electronics and Electrical.
Degree Name:
Ph.D.
Degree Level:
doctoral
Degree Program:
Graduate College; Electrical and Computer Engineering
Degree Grantor:
University of Arizona
Advisor:
Carothers, Jo Dale

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleConcurrent substrate coupling noise modeling and active noise reduction methodology for mixed-signal physical designen_US
dc.creatorLiu, Tingyangen_US
dc.contributor.authorLiu, Tingyangen_US
dc.date.issued1999en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractIn mixed-signal ICs that integrate complex digital circuits together with high-performance analog circuits, signal contamination caused by substrate coupling noise is a critical issue. Fast digital transients can produce noise harmful to the sensitive analog circuits. The noise can be coupled from noisy devices and interconnects into the common substrate and coupled into analog devices. This noise coupling mechanism poses serious challenges toward the signal integrity of the mixed-signal design. The final performance of the ICs signal integrity is heavily dependent on layout schemes and the effectiveness of using noise reduction techniques. A hierarchical substrate coupling noise modeling technique that uses a gate-level lumped parasitic circuit model (for digital circuit layout) and concurrent real-time stimulating waveforms has been developed. This hierarchical approach make the concurrent substrate coupling noise analysis feasible under the current computational resource limitation. The gate-level parasitic extraction can avoid the intensive computation needed by detailed source/drain level modeling technique while keeping a reasonable accuracy with respect to parasitics. The parasitic extraction is also a separate process from the substrate three-dimensional mesh generation process. Therefore, this modeling technique can be easily used for evaluation of different physical design schemes. An innovate active noise reduction method, using the noise cancellation mechanism during the physical design phase to reduce the substrate coupling noise contamination, has also been developed. The fundamental idea of this method is to use the reversely amplified noise to achieve a "virtual" ground for the substrate. The noise is sampled from the substrate and reversely amplified and then re-injected into the substrate, by this method, up to 90% of the original noise can be eliminated. The active substrate coupling noise reduction method has the merit that it can be used together with traditional noise reduction methods such as guard ring deployment. Several test chips have been designed and fabricated to demonstrate the effectiveness of the substrate modeling and reduction methods. In the results section of this dissertation, results from both SPICE-based simulation and measurement from MOSIS 1.2 micron test chips are presented and analyzed.en_US
dc.typetexten_US
dc.typeDissertation-Reproduction (electronic)en_US
dc.subjectEngineering, Electronics and Electrical.en_US
thesis.degree.namePh.D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorCarothers, Jo Daleen_US
dc.identifier.proquest9965937en_US
dc.identifier.bibrecord.b40485754en_US
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