A HIGH VOLTAGE LINEAR COMPATIBLE INTEGRATED INJECTION LOGIC (I2L) STRUCTURE: PROCESS DESIGN AND SPECIFICATIONS

Persistent Link:
http://hdl.handle.net/10150/282891
Title:
A HIGH VOLTAGE LINEAR COMPATIBLE INTEGRATED INJECTION LOGIC (I2L) STRUCTURE: PROCESS DESIGN AND SPECIFICATIONS
Author:
Lalumia, Thomas Mariano
Issue Date:
1980
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
An integrated circuit processing schedule is presented that enables fabrication of both high speed I²L gates and high voltage linear type transistors on the same silicon starting substrate material. This process design circumvents conflicting processing requirements normally encountered in considering an I²L/Linear compatible structure by providing two separate epitaxial thicknesses for the I²L and linear section of the chip. The electrical characteristics of the I²L cells and the linear transistors are presented to illustrate their dependence on the doping conditions and are shown to be in contrast to each other. As a consequence of the separate epitaxial thicknesses, independence of the processing constraints is achieved. Experimental results of linear transistors and I²L devices fabricated using this processing schedule are presented and compared to calculated and computer simulations. Modifications to the basic process design is shown possible and enhanced performance of I²L devices results.
Type:
text; Dissertation-Reproduction (electronic)
Keywords:
Hybrid integrated circuits -- Production control.
Degree Name:
Ph.D.
Degree Level:
doctoral
Degree Program:
Graduate College; Electrical Engineering
Degree Grantor:
University of Arizona

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleA HIGH VOLTAGE LINEAR COMPATIBLE INTEGRATED INJECTION LOGIC (I2L) STRUCTURE: PROCESS DESIGN AND SPECIFICATIONSen_US
dc.creatorLalumia, Thomas Marianoen_US
dc.contributor.authorLalumia, Thomas Marianoen_US
dc.date.issued1980en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractAn integrated circuit processing schedule is presented that enables fabrication of both high speed I²L gates and high voltage linear type transistors on the same silicon starting substrate material. This process design circumvents conflicting processing requirements normally encountered in considering an I²L/Linear compatible structure by providing two separate epitaxial thicknesses for the I²L and linear section of the chip. The electrical characteristics of the I²L cells and the linear transistors are presented to illustrate their dependence on the doping conditions and are shown to be in contrast to each other. As a consequence of the separate epitaxial thicknesses, independence of the processing constraints is achieved. Experimental results of linear transistors and I²L devices fabricated using this processing schedule are presented and compared to calculated and computer simulations. Modifications to the basic process design is shown possible and enhanced performance of I²L devices results.en_US
dc.typetexten_US
dc.typeDissertation-Reproduction (electronic)en_US
dc.subjectHybrid integrated circuits -- Production control.en_US
thesis.degree.namePh.D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical Engineeringen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.identifier.proquest8107163en_US
dc.identifier.oclc8671757en_US
dc.identifier.bibrecord.b13899818en_US
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