A fractal compaction algorithm for efficient power estimation of CMOS designs

Persistent Link:
http://hdl.handle.net/10150/282850
Title:
A fractal compaction algorithm for efficient power estimation of CMOS designs
Author:
Radjassamy, Radjakichenin, 1968.
Issue Date:
1998
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
In this dissertation, a vector compaction technique called the Fractal Compaction Algorithm is presented. The fractal compaction algorithm significantly reduces the time needed for estimating the power consumed in CMOS circuits. CMOS IC design requires accurate power estimation at every level in the design hierarchy. Power estimation methods that are currently available are either dynamic or static. Dynamic methods simulate the design using specific input vector sets and estimate the power consumed. Though accurate, dynamic methods require prohibitively long simulation time for large designs and large vector sets. Static power estimation methods, on the other hand, use analytical tools such as statistics and probability to estimate power. The static methods are usually fast but less accurate. To achieve both speed and accuracy, one approach would be to simulate with a compact vector set that has similar switching behavior as the original vector set. The algorithm presented in this work generates such a compact set using fractal concepts. It exploits the correlation present in the toggle distribution of a circuit's internal nodes for compacting the vector set. Instead of using correlation co-efficients, the fractal algorithm uses a simpler parameter, called the Hurst parameter to quantify correlation. The performance of fractal algorithm with combinational and sequential circuits showed very high compaction that can lead to a shorter design phase and quicker tape out. When compared to previously reported results, the fractal algorithm compacts much higher while keeping the estimation error low.
Type:
text; Dissertation-Reproduction (electronic)
Keywords:
Engineering, Electronics and Electrical.; Computer Science.
Degree Name:
Ph.D.
Degree Level:
doctoral
Degree Program:
Graduate College; Electrical and Computer Engineering
Degree Grantor:
University of Arizona
Advisor:
Carothers, Jo Dale

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleA fractal compaction algorithm for efficient power estimation of CMOS designsen_US
dc.creatorRadjassamy, Radjakichenin, 1968.en_US
dc.contributor.authorRadjassamy, Radjakichenin, 1968.en_US
dc.date.issued1998en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractIn this dissertation, a vector compaction technique called the Fractal Compaction Algorithm is presented. The fractal compaction algorithm significantly reduces the time needed for estimating the power consumed in CMOS circuits. CMOS IC design requires accurate power estimation at every level in the design hierarchy. Power estimation methods that are currently available are either dynamic or static. Dynamic methods simulate the design using specific input vector sets and estimate the power consumed. Though accurate, dynamic methods require prohibitively long simulation time for large designs and large vector sets. Static power estimation methods, on the other hand, use analytical tools such as statistics and probability to estimate power. The static methods are usually fast but less accurate. To achieve both speed and accuracy, one approach would be to simulate with a compact vector set that has similar switching behavior as the original vector set. The algorithm presented in this work generates such a compact set using fractal concepts. It exploits the correlation present in the toggle distribution of a circuit's internal nodes for compacting the vector set. Instead of using correlation co-efficients, the fractal algorithm uses a simpler parameter, called the Hurst parameter to quantify correlation. The performance of fractal algorithm with combinational and sequential circuits showed very high compaction that can lead to a shorter design phase and quicker tape out. When compared to previously reported results, the fractal algorithm compacts much higher while keeping the estimation error low.en_US
dc.typetexten_US
dc.typeDissertation-Reproduction (electronic)en_US
dc.subjectEngineering, Electronics and Electrical.en_US
dc.subjectComputer Science.en_US
thesis.degree.namePh.D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorCarothers, Jo Daleen_US
dc.identifier.proquest9912158en_US
dc.identifier.bibrecord.b39125117en_US
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