Behavioral simulation of digital to analog converters simulation of segmented current steering DAC with utilization of perfect sampling technique

Persistent Link:
http://hdl.handle.net/10150/280331
Title:
Behavioral simulation of digital to analog converters simulation of segmented current steering DAC with utilization of perfect sampling technique
Author:
Warecki, Sylwester
Issue Date:
2003
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
Rapid progress in telecommunication and introduction of wireless phones has revolutionized the way, in which the analog signal is treated. High Radio Frequency (RF) pollution caused by increased number of subscribers imposes new requirements on the quality of transmitted RF signal. These requirements are met by introduction of Digital Direct Synthesis (DDS) of Intermediate Frequency (IF). The DDS eliminates the analog IF mixing stage, which is responsible interference with modulated signal. The high accuracy of DDS modulation is possible only with high quality digital-to-analog conversion. The design of Digital-to-Analog Converters (DAC) providing high-speed and high-resolution is extremely difficult. To overcome problems caused by manufacturing process variation numerous techniques such as thermometer coding or calibration are utilized in DAC design. However, in many cases implementation of these techniques becomes a source of new problems such as clock jitter or glitch. To solve them simulation of DAC, depicting numerous effects of physical phenomena, is an absolute necessity. Unfortunately such simulation with utilization of off-the-shelf mixed signal simulators is very demanding. Therefore simulation of all DAC circuit becomes impractical due to long simulation time or lack of good models of still studied phenomena such as glitch. A novel method allowing for simultaneous and accurate representation of numerous phenomena and significantly increasing simulation speed is proposed. The method is called a Perfect Sampling Technique (PST) and it allows for precise calculation of most important in telecommunication dynamic DAC performance metric---the Spurious Free Dynamic Range (SFDR). The technique was primarily built to overcome the deficiencies of popular Discrete Fourier Transform (DFT). This novel approach allows for concurrent simulation of the following phenomena: deterministic and random clock jitter, random and graded current source mismatch, and the glitch and output finite impedance. The implemented in Visual C++ simulator provides means of representation of various DAC structures: segmentation (thermometer and binary coding), 2D layout of current source matrix and analog switch dynamic characteristics. It utilizes behavioral models of DAC building blocks (analog switches) in custom-built extremely fast event driven simulation framework. It also provides means for parametric, statistical, transient and spectral analysis of DAC.
Type:
text; Dissertation-Reproduction (electronic)
Keywords:
Engineering, Electronics and Electrical.
Degree Name:
Ph.D.
Degree Level:
doctoral
Degree Program:
Graduate College; Electrical and Computer Engineering
Degree Grantor:
University of Arizona
Advisor:
Palusinski, Olgierd A.

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleBehavioral simulation of digital to analog converters simulation of segmented current steering DAC with utilization of perfect sampling techniqueen_US
dc.creatorWarecki, Sylwesteren_US
dc.contributor.authorWarecki, Sylwesteren_US
dc.date.issued2003en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractRapid progress in telecommunication and introduction of wireless phones has revolutionized the way, in which the analog signal is treated. High Radio Frequency (RF) pollution caused by increased number of subscribers imposes new requirements on the quality of transmitted RF signal. These requirements are met by introduction of Digital Direct Synthesis (DDS) of Intermediate Frequency (IF). The DDS eliminates the analog IF mixing stage, which is responsible interference with modulated signal. The high accuracy of DDS modulation is possible only with high quality digital-to-analog conversion. The design of Digital-to-Analog Converters (DAC) providing high-speed and high-resolution is extremely difficult. To overcome problems caused by manufacturing process variation numerous techniques such as thermometer coding or calibration are utilized in DAC design. However, in many cases implementation of these techniques becomes a source of new problems such as clock jitter or glitch. To solve them simulation of DAC, depicting numerous effects of physical phenomena, is an absolute necessity. Unfortunately such simulation with utilization of off-the-shelf mixed signal simulators is very demanding. Therefore simulation of all DAC circuit becomes impractical due to long simulation time or lack of good models of still studied phenomena such as glitch. A novel method allowing for simultaneous and accurate representation of numerous phenomena and significantly increasing simulation speed is proposed. The method is called a Perfect Sampling Technique (PST) and it allows for precise calculation of most important in telecommunication dynamic DAC performance metric---the Spurious Free Dynamic Range (SFDR). The technique was primarily built to overcome the deficiencies of popular Discrete Fourier Transform (DFT). This novel approach allows for concurrent simulation of the following phenomena: deterministic and random clock jitter, random and graded current source mismatch, and the glitch and output finite impedance. The implemented in Visual C++ simulator provides means of representation of various DAC structures: segmentation (thermometer and binary coding), 2D layout of current source matrix and analog switch dynamic characteristics. It utilizes behavioral models of DAC building blocks (analog switches) in custom-built extremely fast event driven simulation framework. It also provides means for parametric, statistical, transient and spectral analysis of DAC.en_US
dc.typetexten_US
dc.typeDissertation-Reproduction (electronic)en_US
dc.subjectEngineering, Electronics and Electrical.en_US
thesis.degree.namePh.D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorPalusinski, Olgierd A.en_US
dc.identifier.proquest3090023en_US
dc.identifier.bibrecord.b44426811en_US
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