Implementation of a Wang algorithm based ATPG for combinational logic circuits

Persistent Link:
http://hdl.handle.net/10150/278231
Title:
Implementation of a Wang algorithm based ATPG for combinational logic circuits
Author:
Cunning, Steven J., 1963-
Issue Date:
1992
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
Automatic Test Pattern Generation (ATPG) is the process of generating tests vectors for a circuit given only the physical description of that circuit. Many of today's ATPG systems are based on the D-Algorithm, PODEM, or FAN. This research is focused on the development and use of a more time efficient ATPG system for combinational logic circuits. The ATPG system developed by this research will be based on the Wang algorithm which uses a 9-value calculus. The fault model used is the single stuck-at fault model. Two versions of the system will be developed. The batch version will attempt to determine tests for all single stuck-at faults in the given circuit. The interactive version will allow the operator to select a single fault to be tested. The system will be written in C and developed for the MS-DOS microcomputer environment.
Type:
text; Thesis-Reproduction (electronic)
Keywords:
Engineering, Electronics and Electrical.; Computer Science.
Degree Name:
M.S.
Degree Level:
masters
Degree Program:
Graduate College
Degree Grantor:
University of Arizona
Advisor:
Hill, Fredrick J.

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleImplementation of a Wang algorithm based ATPG for combinational logic circuitsen_US
dc.creatorCunning, Steven J., 1963-en_US
dc.contributor.authorCunning, Steven J., 1963-en_US
dc.date.issued1992en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractAutomatic Test Pattern Generation (ATPG) is the process of generating tests vectors for a circuit given only the physical description of that circuit. Many of today's ATPG systems are based on the D-Algorithm, PODEM, or FAN. This research is focused on the development and use of a more time efficient ATPG system for combinational logic circuits. The ATPG system developed by this research will be based on the Wang algorithm which uses a 9-value calculus. The fault model used is the single stuck-at fault model. Two versions of the system will be developed. The batch version will attempt to determine tests for all single stuck-at faults in the given circuit. The interactive version will allow the operator to select a single fault to be tested. The system will be written in C and developed for the MS-DOS microcomputer environment.en_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.subjectEngineering, Electronics and Electrical.en_US
dc.subjectComputer Science.en_US
thesis.degree.nameM.S.en_US
thesis.degree.levelmastersen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorHill, Fredrick J.en_US
dc.identifier.proquest1350937en_US
dc.identifier.bibrecord.b26422724en_US
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