Persistent Link:
http://hdl.handle.net/10150/278171
Title:
Signal delay estimates for design of multichip assemblies
Author:
Menezes, Karol Fidelis, 1966-
Issue Date:
1992
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
Signal delay estimates for high-speed interconnection nets are formulated using analytical methods. The equations are suitable for estimating delay in interconnects of printed wiring boards and multi-chip modules where the resistance of wires is small. Effects of drivers, receivers, chip interfaces and wires on delay are considered by using simple models. The wires are treated as lossless transmission lines with capacitive discontinuities modeling receiver chip interfaces. Drivers are voltage sources with series resistance. Signal delay consists of line propagation delay and delay due to the change in rise time and reflections at the discontinuities. Various commonly used net topologies are identified and wiring rules and delay predictors provided for each of them. It is shown that interconnect delay can be formulated as a non-linear function of the product of the line characteristic impedance and load capacitance. SPICE simulations are sued to validate analytical derivations.
Type:
text; Thesis-Reproduction (electronic)
Keywords:
Engineering, Electronics and Electrical.
Degree Name:
M.S.
Degree Level:
masters
Degree Program:
Graduate College
Degree Grantor:
University of Arizona
Advisor:
Palusinski, O. A.

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleSignal delay estimates for design of multichip assembliesen_US
dc.creatorMenezes, Karol Fidelis, 1966-en_US
dc.contributor.authorMenezes, Karol Fidelis, 1966-en_US
dc.date.issued1992en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractSignal delay estimates for high-speed interconnection nets are formulated using analytical methods. The equations are suitable for estimating delay in interconnects of printed wiring boards and multi-chip modules where the resistance of wires is small. Effects of drivers, receivers, chip interfaces and wires on delay are considered by using simple models. The wires are treated as lossless transmission lines with capacitive discontinuities modeling receiver chip interfaces. Drivers are voltage sources with series resistance. Signal delay consists of line propagation delay and delay due to the change in rise time and reflections at the discontinuities. Various commonly used net topologies are identified and wiring rules and delay predictors provided for each of them. It is shown that interconnect delay can be formulated as a non-linear function of the product of the line characteristic impedance and load capacitance. SPICE simulations are sued to validate analytical derivations.en_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.subjectEngineering, Electronics and Electrical.en_US
thesis.degree.nameM.S.en_US
thesis.degree.levelmastersen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorPalusinski, O. A.en_US
dc.identifier.proquest1349453en_US
dc.identifier.bibrecord.b27691202en_US
All Items in UA Campus Repository are protected by copyright, with all rights reserved, unless otherwise indicated.