Persistent Link:
http://hdl.handle.net/10150/278017
Title:
Framework for CMOS standard cell realization of AHPL descriptions
Author:
Jepperson, Brian, 1967-
Issue Date:
1991
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
Hardware description languages can be powerful tools in creating digital system designs. AHPL, A Hardware Programming Language, is a hardware description language that simplifies the task of designing a digital system. One of the major problems in using a hardware description language is interfacing with commercially available simulation and layout tools. Many commercial tools use the Electronic Design Interchange Format (EDIF) in order to communicate designs. This thesis describes the AHPL to EDIF Netlist Translator (AENT) program. By using AENT, a designer can write an AHPL description, verify the design with a function level simulator, and generate a CMOS standard cell layout using a commercial layout tool. A post layout gate level simulation can also be performed to verify timing constraints. Several layout examples are given in this thesis, and results are compared with the Berkeley Synthesis System.
Type:
text; Thesis-Reproduction (electronic)
Keywords:
Engineering, Electronics and Electrical.
Degree Name:
M.S.
Degree Level:
masters
Degree Program:
Graduate College
Degree Grantor:
University of Arizona

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleFramework for CMOS standard cell realization of AHPL descriptionsen_US
dc.creatorJepperson, Brian, 1967-en_US
dc.contributor.authorJepperson, Brian, 1967-en_US
dc.date.issued1991en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractHardware description languages can be powerful tools in creating digital system designs. AHPL, A Hardware Programming Language, is a hardware description language that simplifies the task of designing a digital system. One of the major problems in using a hardware description language is interfacing with commercially available simulation and layout tools. Many commercial tools use the Electronic Design Interchange Format (EDIF) in order to communicate designs. This thesis describes the AHPL to EDIF Netlist Translator (AENT) program. By using AENT, a designer can write an AHPL description, verify the design with a function level simulator, and generate a CMOS standard cell layout using a commercial layout tool. A post layout gate level simulation can also be performed to verify timing constraints. Several layout examples are given in this thesis, and results are compared with the Berkeley Synthesis System.en_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.subjectEngineering, Electronics and Electrical.en_US
thesis.degree.nameM.S.en_US
thesis.degree.levelmastersen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.identifier.proquest1346438en_US
dc.identifier.bibrecord.b27227728en_US
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