Fault tolerance and reconfiguration strategies for tree architectures

Persistent Link:
http://hdl.handle.net/10150/277258
Title:
Fault tolerance and reconfiguration strategies for tree architectures
Author:
Ko, Chen-Ken, 1961-
Issue Date:
1990
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
Reconfigurable binary tree architectures have been widely studied and used in various VLSI implementations. These fault tolerance approaches can be classified into two categories. In thesis, we propose a fault diagnosis for the first category. Then a new block-oriented fault tolerance scheme for tree architectures is presented for the second category. The fundamental idea is to extend each single PE node in the tree to a block. Each block could consist of several PEs and the associated interconnection links. It is shown that several previous fault tolerant designs in the literature are special cases of the proposed design. The VLSI layout of binary tree is very efficient and the problem of long interconnections in other designs has been alleviated. Efficient reconfiguration algorithms and analysis are also presented.
Type:
text; Thesis-Reproduction (electronic)
Keywords:
Computer Science.
Degree Name:
M.S.
Degree Level:
masters
Degree Program:
Graduate College
Degree Grantor:
University of Arizona
Advisor:
Kuo, Sy-Yen

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleFault tolerance and reconfiguration strategies for tree architecturesen_US
dc.creatorKo, Chen-Ken, 1961-en_US
dc.contributor.authorKo, Chen-Ken, 1961-en_US
dc.date.issued1990en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractReconfigurable binary tree architectures have been widely studied and used in various VLSI implementations. These fault tolerance approaches can be classified into two categories. In thesis, we propose a fault diagnosis for the first category. Then a new block-oriented fault tolerance scheme for tree architectures is presented for the second category. The fundamental idea is to extend each single PE node in the tree to a block. Each block could consist of several PEs and the associated interconnection links. It is shown that several previous fault tolerant designs in the literature are special cases of the proposed design. The VLSI layout of binary tree is very efficient and the problem of long interconnections in other designs has been alleviated. Efficient reconfiguration algorithms and analysis are also presented.en_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.subjectComputer Science.en_US
thesis.degree.nameM.S.en_US
thesis.degree.levelmastersen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorKuo, Sy-Yenen_US
dc.identifier.proquest1339887en_US
dc.identifier.bibrecord.b26222176en_US
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