Efficient reconfiguration by degradation in defect-tolerant VLSI arrays

Persistent Link:
http://hdl.handle.net/10150/277195
Title:
Efficient reconfiguration by degradation in defect-tolerant VLSI arrays
Author:
Chen, Ing-yi, 1962-
Issue Date:
1989
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
This thesis addresses the problem of constructing a flawless subarray from a defective VLSI/WSI array consists of identical cells such as memory cells or processors. In contrast to the redundancy approach in which some cells are dedicated as spares, all the cells in the degradation approach are treated in a uniform way. Each cell can be either fault-free or defective and a subarray which contains no faulty cell is derived under constraints of switching and routing mechanisms. Although extensive literatures exist concerning spare allocation and reconfiguration in arrays with redundancy, little research has been published on optimal reconfiguration in a degradable array. A systematic method based on graph theoretic models is developed to deal with the problem. The complexities of reconfiguration are analyzed for schemes using different switching mechanisms. Efficient heuristic algorithms are presented to determine a target subarray from the defective host array.
Type:
text; Thesis-Reproduction (electronic)
Keywords:
Integrated circuits -- Very large scale integration -- Design and construction.
Degree Name:
M.S.
Degree Level:
masters
Degree Program:
Graduate College; Electrical Engineering
Degree Grantor:
University of Arizona
Advisor:
Kuo, Sy-Yen

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleEfficient reconfiguration by degradation in defect-tolerant VLSI arraysen_US
dc.creatorChen, Ing-yi, 1962-en_US
dc.contributor.authorChen, Ing-yi, 1962-en_US
dc.date.issued1989en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractThis thesis addresses the problem of constructing a flawless subarray from a defective VLSI/WSI array consists of identical cells such as memory cells or processors. In contrast to the redundancy approach in which some cells are dedicated as spares, all the cells in the degradation approach are treated in a uniform way. Each cell can be either fault-free or defective and a subarray which contains no faulty cell is derived under constraints of switching and routing mechanisms. Although extensive literatures exist concerning spare allocation and reconfiguration in arrays with redundancy, little research has been published on optimal reconfiguration in a degradable array. A systematic method based on graph theoretic models is developed to deal with the problem. The complexities of reconfiguration are analyzed for schemes using different switching mechanisms. Efficient heuristic algorithms are presented to determine a target subarray from the defective host array.en_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.subjectIntegrated circuits -- Very large scale integration -- Design and construction.en_US
thesis.degree.nameM.S.en_US
thesis.degree.levelmastersen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical Engineeringen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorKuo, Sy-Yenen_US
dc.identifier.proquest1339202en_US
dc.identifier.oclc24479865en_US
dc.identifier.bibrecord.b17878081en_US
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