Persistent Link:
http://hdl.handle.net/10150/277133
Title:
Expandable multiprocessor using low cost microprocessors
Author:
Olson, Joseph Augustine, 1959-
Issue Date:
1989
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
This paper presents an expandable multiprocessor system design based on: (a) an INTEL 80188 based microcomputer as the basic processing element; (b) a multi-channel, multi-access, processor independent interprocessor communications subnetwork with data transfer rates of 250 Kbps or 1 Mbps per channel. The basic system design consists of two IBM PC expansion cards--a single processor IBM PC Interface Card, and a Quad Processor Card containing four 80188 CPUs. Each processor has access to two separate interprocessor (IP) serial data channels. An IP channel supports as many as 16 processors using a token bus data link control. IP communications is either direct or routed via intervening processors to support an unlimited number of processors in a given system.
Type:
text; Thesis-Reproduction (electronic)
Keywords:
Multiprocessors.; Computer engineering.
Degree Name:
M.S.
Degree Level:
masters
Degree Program:
Graduate College; Electrical and Computer Engineering
Degree Grantor:
University of Arizona
Advisor:
Hill, Frederick J.

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleExpandable multiprocessor using low cost microprocessorsen_US
dc.creatorOlson, Joseph Augustine, 1959-en_US
dc.contributor.authorOlson, Joseph Augustine, 1959-en_US
dc.date.issued1989en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractThis paper presents an expandable multiprocessor system design based on: (a) an INTEL 80188 based microcomputer as the basic processing element; (b) a multi-channel, multi-access, processor independent interprocessor communications subnetwork with data transfer rates of 250 Kbps or 1 Mbps per channel. The basic system design consists of two IBM PC expansion cards--a single processor IBM PC Interface Card, and a Quad Processor Card containing four 80188 CPUs. Each processor has access to two separate interprocessor (IP) serial data channels. An IP channel supports as many as 16 processors using a token bus data link control. IP communications is either direct or routed via intervening processors to support an unlimited number of processors in a given system.en_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.subjectMultiprocessors.en_US
dc.subjectComputer engineering.en_US
thesis.degree.nameM.S.en_US
thesis.degree.levelmastersen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorHill, Frederick J.en_US
dc.identifier.proquest1338526en_US
dc.identifier.oclc23612966en_US
dc.identifier.bibrecord.b17649341en_US
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