Analysis domain truncation of interconnections in multilayer packaging structures

Persistent Link:
http://hdl.handle.net/10150/277078
Title:
Analysis domain truncation of interconnections in multilayer packaging structures
Author:
Garg, Nitin Kumar, 1967-
Issue Date:
1989
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
Interconnect lines, which connect components on a chip, can exhibit transmission line properties. Several factors like decrease in size of components, and decrease in spacing between interconnect lines, have contributed to the increase in importance of interconnect lines. A circuit-analysis approach that does not include the effect of these lines may be useless for highly dense chips. The presence of an active line does not require the analysis of all the other lines in a transmission-line system. In this thesis, a numerical experimental approach based on several industry-typical geometries is used to discuss analysis domain truncation of parallel conductors lying on a horizontal plane. It is found that "The maximum analysis domain between parallel conductors lying on a horizontal plane can be deduced from the analysis of the case of several similar, and parallel conductors of smallest possible width lying on a horizontal plane." UAC (University of Arizona Capacitance Calculator) is used as the TEM parameter extractor, while UACSL (University of Arizona Coupled Line Simulator With Linear Terminations) is used to calculate the voltages on the transmission lines.
Type:
text; Thesis-Reproduction (electronic)
Keywords:
Integrated circuits.; Electric interference.
Degree Name:
M.S.
Degree Level:
masters
Degree Program:
Graduate College; Electrical and Computer Engineering
Degree Grantor:
University of Arizona
Advisor:
Prince, John L.

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleAnalysis domain truncation of interconnections in multilayer packaging structuresen_US
dc.creatorGarg, Nitin Kumar, 1967-en_US
dc.contributor.authorGarg, Nitin Kumar, 1967-en_US
dc.date.issued1989en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractInterconnect lines, which connect components on a chip, can exhibit transmission line properties. Several factors like decrease in size of components, and decrease in spacing between interconnect lines, have contributed to the increase in importance of interconnect lines. A circuit-analysis approach that does not include the effect of these lines may be useless for highly dense chips. The presence of an active line does not require the analysis of all the other lines in a transmission-line system. In this thesis, a numerical experimental approach based on several industry-typical geometries is used to discuss analysis domain truncation of parallel conductors lying on a horizontal plane. It is found that "The maximum analysis domain between parallel conductors lying on a horizontal plane can be deduced from the analysis of the case of several similar, and parallel conductors of smallest possible width lying on a horizontal plane." UAC (University of Arizona Capacitance Calculator) is used as the TEM parameter extractor, while UACSL (University of Arizona Coupled Line Simulator With Linear Terminations) is used to calculate the voltages on the transmission lines.en_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.subjectIntegrated circuits.en_US
dc.subjectElectric interference.en_US
thesis.degree.nameM.S.en_US
thesis.degree.levelmastersen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorPrince, John L.en_US
dc.identifier.proquest1337651en_US
dc.identifier.oclc23194247en_US
dc.identifier.bibrecord.b17591533en_US
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