Persistent Link:
http://hdl.handle.net/10150/276973
Title:
Digital system synthesis with standard EDIF output
Author:
Blanton, Ronald DeShawn, 1965-
Issue Date:
1989
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
In the growing field of digital system design, there is a great need for design tools that will assist the engineer in developing large scale systems. AHPL, A Hardware Programming Language, is a hardware description language which allows a digital system to be described, evaluated, and analyzed. But like many design tools, AHPL cannot satisfy the multitude of design tool applications. In order to enhance the power of AHPL as a design tool, an EDIF translator is developed. The EDIF translator generates an EDIF netlist of an AHPL design, thus making it possible to port AHPL designs to other design tools.
Type:
text; Thesis-Reproduction (electronic)
Keywords:
Computer engineering.; Computer hardware description languages.
Degree Name:
M.S.
Degree Level:
masters
Degree Program:
Graduate College; Electrical & Computer Engineering
Degree Grantor:
University of Arizona
Advisor:
Hill, Fredrick J.

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleDigital system synthesis with standard EDIF outputen_US
dc.creatorBlanton, Ronald DeShawn, 1965-en_US
dc.contributor.authorBlanton, Ronald DeShawn, 1965-en_US
dc.date.issued1989en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractIn the growing field of digital system design, there is a great need for design tools that will assist the engineer in developing large scale systems. AHPL, A Hardware Programming Language, is a hardware description language which allows a digital system to be described, evaluated, and analyzed. But like many design tools, AHPL cannot satisfy the multitude of design tool applications. In order to enhance the power of AHPL as a design tool, an EDIF translator is developed. The EDIF translator generates an EDIF netlist of an AHPL design, thus making it possible to port AHPL designs to other design tools.en_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.subjectComputer engineering.en_US
dc.subjectComputer hardware description languages.en_US
thesis.degree.nameM.S.en_US
thesis.degree.levelmastersen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical & Computer Engineeringen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorHill, Fredrick J.en_US
dc.identifier.proquest1336668en_US
dc.identifier.oclc22852873en_US
dc.identifier.bibrecord.b17510569en_US
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