Persistent Link:
http://hdl.handle.net/10150/276959
Title:
THERMAL MODELING/SIMULATION OF LEVEL 1 AND LEVEL 2 VLSI PACKAGING
Author:
Jafar, Mutaz, 1960-
Issue Date:
1986
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Type:
text; Thesis-Reproduction (electronic)
Keywords:
Integrated circuits -- Very large scale integration.
Degree Name:
M.S.
Degree Level:
masters
Degree Program:
Graduate College; Electrical and Computer Engineering
Degree Grantor:
University of Arizona

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleTHERMAL MODELING/SIMULATION OF LEVEL 1 AND LEVEL 2 VLSI PACKAGINGen_US
dc.creatorJafar, Mutaz, 1960-en_US
dc.contributor.authorJafar, Mutaz, 1960-en_US
dc.date.issued1986en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.subjectIntegrated circuits -- Very large scale integration.en_US
thesis.degree.nameM.S.en_US
thesis.degree.levelmastersen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.identifier.proquest1329492en_US
dc.identifier.oclc16749836en_US
dc.identifier.bibrecord.b16141696en_US
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