Persistent Link:
http://hdl.handle.net/10150/276733
Title:
Surface and geometrical effect on the punch-through device
Author:
Liu, Bin, 1957-
Issue Date:
1988
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
The punch-through space-charge-limited load (PTSCLL) may be an alternate VLSI design as a high resistance load device. A surface and geometrical study on the PTSCLL device is presented. From this research, it is found out that the dynamic resistance value increases as the surface bias to a negatively voltage. Also, the resistance increases as the channel length and substrate doping increase. But the resistance value decreases as the channel width, junction depth, and overlap oxide thickness increase. Incorporate these design considerations, it can maximize the resistance value of the PTSCLL.
Type:
text; Thesis-Reproduction (electronic)
Keywords:
Planar transistors.; Integrated circuits.; Semiconductors.
Degree Name:
M.S.
Degree Level:
masters
Degree Program:
Graduate College; Electrical and Computer Engineering
Degree Grantor:
University of Arizona
Advisor:
Mattson, Roy H.

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleSurface and geometrical effect on the punch-through deviceen_US
dc.creatorLiu, Bin, 1957-en_US
dc.contributor.authorLiu, Bin, 1957-en_US
dc.date.issued1988en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractThe punch-through space-charge-limited load (PTSCLL) may be an alternate VLSI design as a high resistance load device. A surface and geometrical study on the PTSCLL device is presented. From this research, it is found out that the dynamic resistance value increases as the surface bias to a negatively voltage. Also, the resistance increases as the channel length and substrate doping increase. But the resistance value decreases as the channel width, junction depth, and overlap oxide thickness increase. Incorporate these design considerations, it can maximize the resistance value of the PTSCLL.en_US
dc.description.noteDigitization note: p.106 missing from paper original; appears to be a pagination error rather than missing content.en
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.subjectPlanar transistors.en_US
dc.subjectIntegrated circuits.en_US
dc.subjectSemiconductors.en_US
thesis.degree.nameM.S.en_US
thesis.degree.levelmastersen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorMattson, Roy H.en_US
dc.identifier.proquest1333605en_US
dc.identifier.oclc20968138en_US
dc.identifier.bibrecord.b18409465en_US
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