The effect of die attach voiding on the thermal resistance of integrated circuit package

Persistent Link:
http://hdl.handle.net/10150/276568
Title:
The effect of die attach voiding on the thermal resistance of integrated circuit package
Author:
Chang, Li-hsin, 1946-
Issue Date:
1987
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
The effect of die attach voiding on the thermal resistance of a hybrid integrated circuit package has been investigated. Voids with precisely controlled geometry, morphology, distribution, and different volume percentages are fabricated in the backside of the silicon chips by modern micro-photolithographic techniques. A large thin film resistor over the entire chip surface area served as a uniform heat generating source. A TO-3 steel package with beryllia substrate is used for chip packaging. Correlation of thermal resistance to power dissipation in the range studied is presented and discussed. The dependence of thermal resistance on void characteristics and total void area are demonstrated through infrared mapping of chip surface temperature; and the correlations are qualitatively analyzed. A brief discussion on die bond void reduction is also given.
Type:
text; Thesis-Reproduction (electronic)
Keywords:
Integrated circuits -- Design.; Heat -- Transmission.
Degree Name:
M.S.
Degree Level:
masters
Degree Program:
Graduate College; Electrical and Computer Engineering
Degree Grantor:
University of Arizona
Advisor:
Johnson, Barry C.

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleThe effect of die attach voiding on the thermal resistance of integrated circuit packageen_US
dc.creatorChang, Li-hsin, 1946-en_US
dc.contributor.authorChang, Li-hsin, 1946-en_US
dc.date.issued1987en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractThe effect of die attach voiding on the thermal resistance of a hybrid integrated circuit package has been investigated. Voids with precisely controlled geometry, morphology, distribution, and different volume percentages are fabricated in the backside of the silicon chips by modern micro-photolithographic techniques. A large thin film resistor over the entire chip surface area served as a uniform heat generating source. A TO-3 steel package with beryllia substrate is used for chip packaging. Correlation of thermal resistance to power dissipation in the range studied is presented and discussed. The dependence of thermal resistance on void characteristics and total void area are demonstrated through infrared mapping of chip surface temperature; and the correlations are qualitatively analyzed. A brief discussion on die bond void reduction is also given.en_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.subjectIntegrated circuits -- Design.en_US
dc.subjectHeat -- Transmission.en_US
thesis.degree.nameM.S.en_US
thesis.degree.levelmastersen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorJohnson, Barry C.en_US
dc.identifier.proquest1332412en_US
dc.identifier.oclc19534408en_US
dc.identifier.bibrecord.b16796706en_US
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