RTL AND SWITCH-LEVEL SIMULATION COMPARISON ON EIGHT BIT MICROPROCESSOR

Persistent Link:
http://hdl.handle.net/10150/276532
Title:
RTL AND SWITCH-LEVEL SIMULATION COMPARISON ON EIGHT BIT MICROPROCESSOR
Author:
Lai, Jiunn-Yiing, 1958-
Issue Date:
1987
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
In this research, an AHPL (A Hardware Programming Language) based automation system is used to design and verify the Intel-8080 microprocessor from the RTL (Register Transfer Level) hardware description through the network list of transistors. The HPSIM is used as a RTL simulator which interprets the AHPL description and executes the connections, branches, and register transfer, and prints line or register values for each circuit clock period. After the AHPL description has been translated to switch-level link list, ESIM is applied for more detailed simulation to ensure the digital behavior in this microprocessor design is correct. The ESIM is an event-driven switch-level simulator which accepts commands from the user, and executes each command before reading the next one. After performing these different levels of simulations, a comparison is discussed at the end.
Type:
text; Thesis-Reproduction (electronic)
Keywords:
Computer hardware description languages.; Computer simulation.
Degree Name:
M.S.
Degree Level:
masters
Degree Program:
Graduate College; Electrical and Computer Engineering
Degree Grantor:
University of Arizona

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleRTL AND SWITCH-LEVEL SIMULATION COMPARISON ON EIGHT BIT MICROPROCESSORen_US
dc.creatorLai, Jiunn-Yiing, 1958-en_US
dc.contributor.authorLai, Jiunn-Yiing, 1958-en_US
dc.date.issued1987en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractIn this research, an AHPL (A Hardware Programming Language) based automation system is used to design and verify the Intel-8080 microprocessor from the RTL (Register Transfer Level) hardware description through the network list of transistors. The HPSIM is used as a RTL simulator which interprets the AHPL description and executes the connections, branches, and register transfer, and prints line or register values for each circuit clock period. After the AHPL description has been translated to switch-level link list, ESIM is applied for more detailed simulation to ensure the digital behavior in this microprocessor design is correct. The ESIM is an event-driven switch-level simulator which accepts commands from the user, and executes each command before reading the next one. After performing these different levels of simulations, a comparison is discussed at the end.en_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.subjectComputer hardware description languages.en_US
dc.subjectComputer simulation.en_US
thesis.degree.nameM.S.en_US
thesis.degree.levelmastersen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.identifier.proquest1332159en_US
dc.identifier.oclc18152742en_US
dc.identifier.bibrecord.b16482396en_US
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