THE IMPLEMENTATION OF THE HIERARCHICAL ABSTRACT SIMULATOR ON THE IPSC COMPUTER

Persistent Link:
http://hdl.handle.net/10150/276519
Title:
THE IMPLEMENTATION OF THE HIERARCHICAL ABSTRACT SIMULATOR ON THE IPSC COMPUTER
Author:
Wang, Yung-Hsin, 1957-
Issue Date:
1987
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
The hierarchical abstract simulator is a multicomponent, multilevel discrete event model where each processor communicates with other processors by message passing. A methodology was developed to map the hierarchical abstract simulator onto distributed simulator architectures. The Intel's Personal Super Computer (iPSC) family with a concurrent-processing architecture is well suited for such simulation implementation. This thesis presents an alternative mapping realization of the hierarchical abstract simulator by using Intel's FORTRAN 286, FORTRAN 77 with extensions, on the iPSC computer (Hypercube). Algorithms for the hierarchical abstract simulator are provided in high level pseudo codes. A summary of iPSC system overview and programming concepts is described. Also, two examples are given for the illustration of our hypercube implementation. Finally, some experimental runs were made on the implementation, and comparisons of the performance (execution time) between sequential and parallel processor assignment are made.
Type:
text; Thesis-Reproduction (electronic)
Keywords:
Computer simulation.
Degree Name:
M.S.
Degree Level:
masters
Degree Program:
Graduate College; Electrical and Computer Engineering
Degree Grantor:
University of Arizona

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titleTHE IMPLEMENTATION OF THE HIERARCHICAL ABSTRACT SIMULATOR ON THE IPSC COMPUTERen_US
dc.creatorWang, Yung-Hsin, 1957-en_US
dc.contributor.authorWang, Yung-Hsin, 1957-en_US
dc.date.issued1987en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractThe hierarchical abstract simulator is a multicomponent, multilevel discrete event model where each processor communicates with other processors by message passing. A methodology was developed to map the hierarchical abstract simulator onto distributed simulator architectures. The Intel's Personal Super Computer (iPSC) family with a concurrent-processing architecture is well suited for such simulation implementation. This thesis presents an alternative mapping realization of the hierarchical abstract simulator by using Intel's FORTRAN 286, FORTRAN 77 with extensions, on the iPSC computer (Hypercube). Algorithms for the hierarchical abstract simulator are provided in high level pseudo codes. A summary of iPSC system overview and programming concepts is described. Also, two examples are given for the illustration of our hypercube implementation. Finally, some experimental runs were made on the implementation, and comparisons of the performance (execution time) between sequential and parallel processor assignment are made.en_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.subjectComputer simulation.en_US
thesis.degree.nameM.S.en_US
thesis.degree.levelmastersen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.identifier.proquest1331477en_US
dc.identifier.oclc17497344en_US
dc.identifier.bibrecord.b16311759en_US
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