PERFORMANCE OF HIERARCHICALLY FLEXIBLE ADAPTIVE COMPUTER ARCHITECTURE APPLIED TO SORTING PROBLEMS

Persistent Link:
http://hdl.handle.net/10150/276457
Title:
PERFORMANCE OF HIERARCHICALLY FLEXIBLE ADAPTIVE COMPUTER ARCHITECTURE APPLIED TO SORTING PROBLEMS
Author:
Ferng, Ming-Jehn, 1958-
Issue Date:
1987
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
In this thesis existing models of adaptive computer architecture were modified to adapt actual sorting problems to "divide 'n' conquer" (DQ) coordinator type configuration in which the children processors were expanded from three to four. Two hire/fire strategies, one using packets waiting in queue and the other using the average turn around time, were applied to maintain the hierarchical tree structure. More than 1200 simulation runs were analyzed and compared, finding that the first strategy was best at fast packet arrival rate and the second strategy was best at slow packets arrival rate. Comparing the hire/fire signal generation policies, the "fc-root" was best and the "root-fp" was worst. While comparing the effect of variable weighting factors in processors, using smaller weighting factor in either "partitioner" for the first strategy or "f-computer" for the second strategy may improve the system performance. (Abstract shortened with permission of author.)
Type:
text; Thesis-Reproduction (electronic)
Keywords:
Computer architecture.; Computer simulation.; Sorting (Electronic computers)
Degree Name:
M.S.
Degree Level:
masters
Degree Program:
Graduate College; Electrical and Computer Engineering
Degree Grantor:
University of Arizona

Full metadata record

DC FieldValue Language
dc.language.isoen_USen_US
dc.titlePERFORMANCE OF HIERARCHICALLY FLEXIBLE ADAPTIVE COMPUTER ARCHITECTURE APPLIED TO SORTING PROBLEMSen_US
dc.creatorFerng, Ming-Jehn, 1958-en_US
dc.contributor.authorFerng, Ming-Jehn, 1958-en_US
dc.date.issued1987en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractIn this thesis existing models of adaptive computer architecture were modified to adapt actual sorting problems to "divide 'n' conquer" (DQ) coordinator type configuration in which the children processors were expanded from three to four. Two hire/fire strategies, one using packets waiting in queue and the other using the average turn around time, were applied to maintain the hierarchical tree structure. More than 1200 simulation runs were analyzed and compared, finding that the first strategy was best at fast packet arrival rate and the second strategy was best at slow packets arrival rate. Comparing the hire/fire signal generation policies, the "fc-root" was best and the "root-fp" was worst. While comparing the effect of variable weighting factors in processors, using smaller weighting factor in either "partitioner" for the first strategy or "f-computer" for the second strategy may improve the system performance. (Abstract shortened with permission of author.)en_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.subjectComputer architecture.en_US
dc.subjectComputer simulation.en_US
dc.subjectSorting (Electronic computers)en_US
thesis.degree.nameM.S.en_US
thesis.degree.levelmastersen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.identifier.proquest1331399en_US
dc.identifier.oclc18037509en_US
dc.identifier.bibrecord.b18371310en_US
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