ROBUST DEVICE MODELING WITH PROCESS VARIATION CONSIDERATION AND DIMENSION REDUCTION TECHNIQUES

Persistent Link:
http://hdl.handle.net/10150/194092
Title:
ROBUST DEVICE MODELING WITH PROCESS VARIATION CONSIDERATION AND DIMENSION REDUCTION TECHNIQUES
Author:
Mitev, Alexander
Issue Date:
2009
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
Nowadays the highest device integration affects the design process in several ways. The process variations (PV) significantly impact the circuit performance. As a consequence, a major consideration is determining the relation of the production yield to the technology based manufacturing variations. The traditional Monte Carlo based sampling analysis became computationally not effective due to employing complex device models with the large parameter set. The higher device integration requires dealing with numerous local and global parameters and can bottleneck the efforts of achieving fast design cycles.Statistical analysis can be facilitated by direct relation estimation a of circuit metrics to the set of PV parameters. The traditional transistor models use a large number of parameters and equations but various performance factors are possible to be related to small parameter set. A new macro model is proposed for CMOS complementary gates, where all static and dynamic characteristics are related to set of Finite Points of IV device curves. All timing and power related quantities can be predicted by evaluating the model equations. The dynamic characterization relies on charge distribution at each node. The affect of all PV is represented with characterizing the FP sensitivity. In overall the new gate model employ same computational structure for different devices in far more simple computational form.Large scale circuit analysis based on the FP models can be used for estimation of various global performance parameters. Timing performance (STA) is calculated from node to node, where at each step a new set of parameters (including PV) are introduced. Motivated by the limitations the traditional PCA, we simplify the overall computational cost with new efficient reduction technique. It turned out that the input output correlation of performance-parameters model is essential information for reduction. If the model is unknown, Sliced Inverse Regression (SIR) technique can be used to determine the Effective Reduction Space (e.d.r.). Optionally if the empiric performance analytic expression is known, the e.d.r. is found by Principle Hessian Method. In theoretical aspect the inverse reduction technique reduces parameters in the sense of their statistical significance.
Type:
text; Electronic Dissertation
Keywords:
Circuits; Model Order Reduction; Modeling; Process Variation; Simulation
Degree Name:
Ph.D.
Degree Level:
doctoral
Degree Program:
Electrical & Computer Engineering; Graduate College
Degree Grantor:
University of Arizona
Advisor:
Wang, Janet; Marefat, Michael
Committee Chair:
Wang, Janet; Marefat, Michael

Full metadata record

DC FieldValue Language
dc.language.isoENen_US
dc.titleROBUST DEVICE MODELING WITH PROCESS VARIATION CONSIDERATION AND DIMENSION REDUCTION TECHNIQUESen_US
dc.creatorMitev, Alexanderen_US
dc.contributor.authorMitev, Alexanderen_US
dc.date.issued2009en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractNowadays the highest device integration affects the design process in several ways. The process variations (PV) significantly impact the circuit performance. As a consequence, a major consideration is determining the relation of the production yield to the technology based manufacturing variations. The traditional Monte Carlo based sampling analysis became computationally not effective due to employing complex device models with the large parameter set. The higher device integration requires dealing with numerous local and global parameters and can bottleneck the efforts of achieving fast design cycles.Statistical analysis can be facilitated by direct relation estimation a of circuit metrics to the set of PV parameters. The traditional transistor models use a large number of parameters and equations but various performance factors are possible to be related to small parameter set. A new macro model is proposed for CMOS complementary gates, where all static and dynamic characteristics are related to set of Finite Points of IV device curves. All timing and power related quantities can be predicted by evaluating the model equations. The dynamic characterization relies on charge distribution at each node. The affect of all PV is represented with characterizing the FP sensitivity. In overall the new gate model employ same computational structure for different devices in far more simple computational form.Large scale circuit analysis based on the FP models can be used for estimation of various global performance parameters. Timing performance (STA) is calculated from node to node, where at each step a new set of parameters (including PV) are introduced. Motivated by the limitations the traditional PCA, we simplify the overall computational cost with new efficient reduction technique. It turned out that the input output correlation of performance-parameters model is essential information for reduction. If the model is unknown, Sliced Inverse Regression (SIR) technique can be used to determine the Effective Reduction Space (e.d.r.). Optionally if the empiric performance analytic expression is known, the e.d.r. is found by Principle Hessian Method. In theoretical aspect the inverse reduction technique reduces parameters in the sense of their statistical significance.en_US
dc.typetexten_US
dc.typeElectronic Dissertationen_US
dc.subjectCircuitsen_US
dc.subjectModel Order Reductionen_US
dc.subjectModelingen_US
dc.subjectProcess Variationen_US
dc.subjectSimulationen_US
thesis.degree.namePh.D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineElectrical & Computer Engineeringen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorWang, Janeten_US
dc.contributor.advisorMarefat, Michaelen_US
dc.contributor.chairWang, Janeten_US
dc.contributor.chairMarefat, Michaelen_US
dc.contributor.committeememberWang, Janeten_US
dc.contributor.committeememberMarefat, Michaelen_US
dc.contributor.committeememberLysecky, Susanen_US
dc.contributor.committeememberLopes, Leonardoen_US
dc.identifier.proquest10548en_US
dc.identifier.oclc659752287en_US
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