Microarchitecture and Compiler Techniques for Dual Width ISA Processors

Persistent Link:
http://hdl.handle.net/10150/193726
Title:
Microarchitecture and Compiler Techniques for Dual Width ISA Processors
Author:
Krishnaswamy, Arvind
Issue Date:
2006
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
Embedded processors have to execute programs under the constraints of limited resources such as memory and power. As a result, code size becomes as important a metric as performance when evaluating applications written for the embedded domain. Existing techniques improve one program metric at the cost of the other. Simultaneouslyachieving good code size and performance is a challenging problem. This dissertation proposes compiler and microarchitectural techniquesthat address this problem.Dual-Width ISA processors provide a platform with two instructionsets - a 32-bit instruction set yielding fast programs and a 16-bit instruction set yielding small programs. The techniques described here exploit properties of dual-width ISA processors to bridge the gap betweenthe small programs and the fast programs by improving the performance of 16-bit programs, yielding small {\em and} fast programs.An integrated microarchitectural/compiler framework (Dynamic InstructionCoalescing) and a purely microarchitectural framework (Dynamic Eager Execution) are proposed. Dynamic Instruction Coalescing introduces a new kindof instruction - an Augmenting eXtension or AX. AX instructions aredynamically coalesced with the succeeding instruction at no cost. Efficient compiler techniques are proposed to use AX instructions to perform localand global optimizations that improve performance without negatively affectingcode size. Dynamic Eager Execution is a microarchitecture that improves the performance of 16-bit programs by eagerly executing instructions. This framework comprises two techniques namely Dynamic Delayed Branching and Dynamic 2-wide Execution. The first improves branch behavior and the otherseeks to improve program execution by simultaneously issuing multiple instructions.
Type:
text; Electronic Dissertation
Degree Name:
PhD
Degree Level:
doctoral
Degree Program:
Computer Science; Graduate College
Degree Grantor:
University of Arizona
Advisor:
Gupta, Rajiv
Committee Chair:
Gupta, Rajiv

Full metadata record

DC FieldValue Language
dc.language.isoENen_US
dc.titleMicroarchitecture and Compiler Techniques for Dual Width ISA Processorsen_US
dc.creatorKrishnaswamy, Arvinden_US
dc.contributor.authorKrishnaswamy, Arvinden_US
dc.date.issued2006en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractEmbedded processors have to execute programs under the constraints of limited resources such as memory and power. As a result, code size becomes as important a metric as performance when evaluating applications written for the embedded domain. Existing techniques improve one program metric at the cost of the other. Simultaneouslyachieving good code size and performance is a challenging problem. This dissertation proposes compiler and microarchitectural techniquesthat address this problem.Dual-Width ISA processors provide a platform with two instructionsets - a 32-bit instruction set yielding fast programs and a 16-bit instruction set yielding small programs. The techniques described here exploit properties of dual-width ISA processors to bridge the gap betweenthe small programs and the fast programs by improving the performance of 16-bit programs, yielding small {\em and} fast programs.An integrated microarchitectural/compiler framework (Dynamic InstructionCoalescing) and a purely microarchitectural framework (Dynamic Eager Execution) are proposed. Dynamic Instruction Coalescing introduces a new kindof instruction - an Augmenting eXtension or AX. AX instructions aredynamically coalesced with the succeeding instruction at no cost. Efficient compiler techniques are proposed to use AX instructions to perform localand global optimizations that improve performance without negatively affectingcode size. Dynamic Eager Execution is a microarchitecture that improves the performance of 16-bit programs by eagerly executing instructions. This framework comprises two techniques namely Dynamic Delayed Branching and Dynamic 2-wide Execution. The first improves branch behavior and the otherseeks to improve program execution by simultaneously issuing multiple instructions.en_US
dc.typetexten_US
dc.typeElectronic Dissertationen_US
thesis.degree.namePhDen_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineComputer Scienceen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorGupta, Rajiven_US
dc.contributor.chairGupta, Rajiven_US
dc.contributor.committeememberRozenblit, Jerzyen_US
dc.contributor.committeememberDowney, Peteren_US
dc.contributor.committeememberDebray, Saumya K.en_US
dc.identifier.proquest1658en_US
dc.identifier.oclc659747465en_US
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