RAPID: Reconfigurable All-Photonic Interconnect for Parallel and Distributed Computers

Persistent Link:
http://hdl.handle.net/10150/193704
Title:
RAPID: Reconfigurable All-Photonic Interconnect for Parallel and Distributed Computers
Author:
Kodi, Avinash Karanth
Issue Date:
2006
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
The relentless quest for processing speeds in the range of Teraflops and beyond has accelerated the need for scalable, parallel, High-Performance Computing (HPC) systems. For these systems to be scalable and attain the desirable performance, the interconnection network connecting the processors, must itself be scalable in both size and bandwidth. However, at higher bit rates and longer communication distances, fundamental electrical signaling limitations reduce the inter-processor communication bandwidth while increasing the power dissipation, thereby affecting not only the performance of HPC systems, but also their scalability.In this dissertation, we propose an optical interconnect based architecture for HPC systems called RAPID (Reconfigurable All Photonic Interconnect for Distributed and parallel systems) that maximizes the bandwidth density, optimizes power consumption and enhances scalability using static wavelength allocation. We also present two cost-effective design alternatives of the architecture, a modified version called M-RAPID and an extended version called E-RAPID that minimizes the cost of the interconnect based on the number of transmitters required. In addition, we propose a detailed implementation and integration methodology of RAPID using current complimentary-metal-oxide-semiconductor (CMOS) technology.In order to develop a flexible interconnection architecture, we provide dynamic system reconfiguration that further reduces the communication bottlenecks and achieves better resource utilization. Reconfigurability is realized by monitoring traffic intensities, and implementing dynamic bandwidth re-allocation (DBR) techniques that adapt to changes in communication patterns. A DBR technique - Lock-Step (LS) that balances the load on each communication channel based on past utilization is also presented.While computer-aided design (CAD) tools have significantly assisted electronic system simulation, the field of system level opto-electronics modeling has lagged behind due to lack of simulation methodologies and tools. We present the design space of developing OPTISIM, a system level modeling and simulation methodology of optical interconnects for HPC systems. Using OPTISIM, we performed detailed simulation of RAPID architectures and compared it to several electrical HPC interconnects using synthetic traffic patterns. Simulation results indicate that the reconfigured architecture shows 35% increased throughput and 20% reduced network latency as compared to HPC electrical networks.
Type:
text; Electronic Dissertation
Degree Name:
PhD
Degree Level:
doctoral
Degree Program:
Electrical & Computer Engineering; Graduate College
Degree Grantor:
University of Arizona
Advisor:
Louri, Ahmed
Committee Chair:
Louri, Ahmed

Full metadata record

DC FieldValue Language
dc.language.isoENen_US
dc.titleRAPID: Reconfigurable All-Photonic Interconnect for Parallel and Distributed Computersen_US
dc.creatorKodi, Avinash Karanthen_US
dc.contributor.authorKodi, Avinash Karanthen_US
dc.date.issued2006en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractThe relentless quest for processing speeds in the range of Teraflops and beyond has accelerated the need for scalable, parallel, High-Performance Computing (HPC) systems. For these systems to be scalable and attain the desirable performance, the interconnection network connecting the processors, must itself be scalable in both size and bandwidth. However, at higher bit rates and longer communication distances, fundamental electrical signaling limitations reduce the inter-processor communication bandwidth while increasing the power dissipation, thereby affecting not only the performance of HPC systems, but also their scalability.In this dissertation, we propose an optical interconnect based architecture for HPC systems called RAPID (Reconfigurable All Photonic Interconnect for Distributed and parallel systems) that maximizes the bandwidth density, optimizes power consumption and enhances scalability using static wavelength allocation. We also present two cost-effective design alternatives of the architecture, a modified version called M-RAPID and an extended version called E-RAPID that minimizes the cost of the interconnect based on the number of transmitters required. In addition, we propose a detailed implementation and integration methodology of RAPID using current complimentary-metal-oxide-semiconductor (CMOS) technology.In order to develop a flexible interconnection architecture, we provide dynamic system reconfiguration that further reduces the communication bottlenecks and achieves better resource utilization. Reconfigurability is realized by monitoring traffic intensities, and implementing dynamic bandwidth re-allocation (DBR) techniques that adapt to changes in communication patterns. A DBR technique - Lock-Step (LS) that balances the load on each communication channel based on past utilization is also presented.While computer-aided design (CAD) tools have significantly assisted electronic system simulation, the field of system level opto-electronics modeling has lagged behind due to lack of simulation methodologies and tools. We present the design space of developing OPTISIM, a system level modeling and simulation methodology of optical interconnects for HPC systems. Using OPTISIM, we performed detailed simulation of RAPID architectures and compared it to several electrical HPC interconnects using synthetic traffic patterns. Simulation results indicate that the reconfigured architecture shows 35% increased throughput and 20% reduced network latency as compared to HPC electrical networks.en_US
dc.typetexten_US
dc.typeElectronic Dissertationen_US
thesis.degree.namePhDen_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineElectrical & Computer Engineeringen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorLouri, Ahmeden_US
dc.contributor.chairLouri, Ahmeden_US
dc.contributor.committeememberHariri, Salimen_US
dc.contributor.committeememberRamasubramanian, Srinivasanen_US
dc.identifier.proquest1671en_US
dc.identifier.oclc659747468en_US
All Items in UA Campus Repository are protected by copyright, with all rights reserved, unless otherwise indicated.