Estimation of Jitter Effects in Oscillators and Frequency Synthesizers Due to Prototypical Perturbation Sources

Persistent Link:
http://hdl.handle.net/10150/193520
Title:
Estimation of Jitter Effects in Oscillators and Frequency Synthesizers Due to Prototypical Perturbation Sources
Author:
Janczak, Teresa Krystyna
Issue Date:
2005
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
The Phase Locked Loops (PLLs) are widely used in contemporary electronic systems for frequency synthesis, clock recovery, frequency multiplication and other purposes. Because of continuous increase in operating frequency of clocking systems the requirements on the clock spectral purity and low jitter became very demanding and are one of major designers' concerns.Frequency synthesizers used in microprocessors are integrated on the same substrate as the rest of the circuit and thus suffer from a substantial switching noise injected into global supply and ground busses. Usually when the reference signal comes from a crystal oscillator, VCO becomes a main source of phase noise. A designer of VCO needs to determine the best circuit structure by considering different prototypical perturbations scenarios and predicting the worst case and jitter response when the perturbation signals are switched on and off. Therefore the time efficient estimation of the jitter effects resulting from many shapes, frequencies and phases of perturbation is critical.The presented dissertation demonstrates simulation methodology for rapid estimation of jitter in oscillators, particularly in VCOs, caused by perturbation sources such as power supply and substrate couplings. The methodology is also extended to these types of PLLs in which the VCO instability is a main contributor to the output timing jitter.Simulation of oscillatory circuits is strongly effected by the round-off errors. Special technique was developed to eliminate these effects.The technique is applicable for predicting timing non-idealities for arbitrary perturbation shapes, frequencies and phases. Different jitter metrics can be easily extracted for all important perturbation scenarios.The methodology utilizes the new concept of the transient multi-cycle Voltage Impulse Sensitivity Function (VISF), which has been developed in the dissertation. It contains information about sensitivity of oscillator to noise injection and also allows for efficient prediction of the transient effects caused by switching on and off the perturbation sources. The methodology offers efficiency and great simplicity of use, which frees designers from complicated, time consuming analysis of data generated by a simulator. The very involved postprocessing of simulation data can be fully automated.
Type:
text; Electronic Dissertation
Keywords:
Voltage Controlled Oscillators; Phase Locked Loops; Electronic circuits -noise; Electronic circuits - simulation; Jitter
Degree Name:
PhD
Degree Level:
doctoral
Degree Program:
Electrical & Computer Engineering; Graduate College
Degree Grantor:
University of Arizona
Advisor:
Palusinski, Olgierd A.
Committee Chair:
Palusinski, Olgierd A.

Full metadata record

DC FieldValue Language
dc.language.isoENen_US
dc.titleEstimation of Jitter Effects in Oscillators and Frequency Synthesizers Due to Prototypical Perturbation Sourcesen_US
dc.creatorJanczak, Teresa Krystynaen_US
dc.contributor.authorJanczak, Teresa Krystynaen_US
dc.date.issued2005en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractThe Phase Locked Loops (PLLs) are widely used in contemporary electronic systems for frequency synthesis, clock recovery, frequency multiplication and other purposes. Because of continuous increase in operating frequency of clocking systems the requirements on the clock spectral purity and low jitter became very demanding and are one of major designers' concerns.Frequency synthesizers used in microprocessors are integrated on the same substrate as the rest of the circuit and thus suffer from a substantial switching noise injected into global supply and ground busses. Usually when the reference signal comes from a crystal oscillator, VCO becomes a main source of phase noise. A designer of VCO needs to determine the best circuit structure by considering different prototypical perturbations scenarios and predicting the worst case and jitter response when the perturbation signals are switched on and off. Therefore the time efficient estimation of the jitter effects resulting from many shapes, frequencies and phases of perturbation is critical.The presented dissertation demonstrates simulation methodology for rapid estimation of jitter in oscillators, particularly in VCOs, caused by perturbation sources such as power supply and substrate couplings. The methodology is also extended to these types of PLLs in which the VCO instability is a main contributor to the output timing jitter.Simulation of oscillatory circuits is strongly effected by the round-off errors. Special technique was developed to eliminate these effects.The technique is applicable for predicting timing non-idealities for arbitrary perturbation shapes, frequencies and phases. Different jitter metrics can be easily extracted for all important perturbation scenarios.The methodology utilizes the new concept of the transient multi-cycle Voltage Impulse Sensitivity Function (VISF), which has been developed in the dissertation. It contains information about sensitivity of oscillator to noise injection and also allows for efficient prediction of the transient effects caused by switching on and off the perturbation sources. The methodology offers efficiency and great simplicity of use, which frees designers from complicated, time consuming analysis of data generated by a simulator. The very involved postprocessing of simulation data can be fully automated.en_US
dc.typetexten_US
dc.typeElectronic Dissertationen_US
dc.subjectVoltage Controlled Oscillatorsen_US
dc.subjectPhase Locked Loopsen_US
dc.subjectElectronic circuits -noiseen_US
dc.subjectElectronic circuits - simulationen_US
dc.subjectJitteren_US
thesis.degree.namePhDen_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineElectrical & Computer Engineeringen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorPalusinski, Olgierd A.en_US
dc.contributor.chairPalusinski, Olgierd A.en_US
dc.contributor.committeememberRozenblit, Jerzy W.en_US
dc.contributor.committeememberVasic, Baneen_US
dc.identifier.proquest1094en_US
dc.identifier.oclc137353951en_US
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