INTELLIGENCE DRIVEN TEST SEQUENCE GENERATOR FOR VLSI (VECTOR, AUTOMATIC TESTING, SCAN DESIGN, FAULT SIMULATION, HEURISTIC SEARCH).

Persistent Link:
http://hdl.handle.net/10150/187889
Title:
INTELLIGENCE DRIVEN TEST SEQUENCE GENERATOR FOR VLSI (VECTOR, AUTOMATIC TESTING, SCAN DESIGN, FAULT SIMULATION, HEURISTIC SEARCH).
Author:
MOHSSENIBEHBAHANI, ALAA.
Issue Date:
1984
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
The era of VLSI design necessitates the development of advanced Computer Aided Design tools. The main objective of this research was to introduce an intelligent automatic Sequential Circuit Test System, SCIRTSS, driven by A Hardware Programming Language, AHPL. SCIRTSS can handle the test vector generation process for VLSI circuits in an early state of the design loop, even before the generation of the final technology dependent network logic list. The driving force of the test generation process is the intelligent search program. The search program, supported by a set of heuristics and an accurate function level simulator, generates the test sequence to propagate the single fault effect to a primary output of the circuit. The test sequence generated is a concatenation of the sequences generated by the repeated searches on the state-space of the design. These sequences are verified by a parallel fault simulator. Design for testability techniques could be used to improve the test sequence generated. This system is user friendly and protable. Several circuits were tested under SCIRTSS, the results of some of them were introduced in this paper.
Type:
text; Dissertation-Reproduction (electronic)
Keywords:
Computer-aided design.; Digital integrated circuits -- Testing.
Degree Name:
Ph.D.
Degree Level:
doctoral
Degree Program:
Electrical and Computer Engineering; Graduate College
Degree Grantor:
University of Arizona
Advisor:
Hill, Frederick

Full metadata record

DC FieldValue Language
dc.language.isoenen_US
dc.titleINTELLIGENCE DRIVEN TEST SEQUENCE GENERATOR FOR VLSI (VECTOR, AUTOMATIC TESTING, SCAN DESIGN, FAULT SIMULATION, HEURISTIC SEARCH).en_US
dc.creatorMOHSSENIBEHBAHANI, ALAA.en_US
dc.contributor.authorMOHSSENIBEHBAHANI, ALAA.en_US
dc.date.issued1984en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractThe era of VLSI design necessitates the development of advanced Computer Aided Design tools. The main objective of this research was to introduce an intelligent automatic Sequential Circuit Test System, SCIRTSS, driven by A Hardware Programming Language, AHPL. SCIRTSS can handle the test vector generation process for VLSI circuits in an early state of the design loop, even before the generation of the final technology dependent network logic list. The driving force of the test generation process is the intelligent search program. The search program, supported by a set of heuristics and an accurate function level simulator, generates the test sequence to propagate the single fault effect to a primary output of the circuit. The test sequence generated is a concatenation of the sequences generated by the repeated searches on the state-space of the design. These sequences are verified by a parallel fault simulator. Design for testability techniques could be used to improve the test sequence generated. This system is user friendly and protable. Several circuits were tested under SCIRTSS, the results of some of them were introduced in this paper.en_US
dc.typetexten_US
dc.typeDissertation-Reproduction (electronic)en_US
dc.subjectComputer-aided design.en_US
dc.subjectDigital integrated circuits -- Testing.en_US
thesis.degree.namePh.D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorHill, Fredericken_US
dc.identifier.proquest8505237en_US
dc.identifier.oclc693589730en_US
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