Persistent Link:
http://hdl.handle.net/10150/187701
Title:
AN OPTIMIZATION STAGE FOR AHPL COMPILER (LAYOUT).
Author:
MAITAN, JACEK.
Issue Date:
1984
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
The dissertation is a description of an analysis and a case study of an Optimization Stage for a Standard Cell oriented silicon compiler. Using the AHPL hardware description language, a complete representation hierarchy (functional, logic, and layout) is proposed for circuits defined at a Register Transfer level. The design of a new class of methods for layout analysis and optimization is based on this hierarchy. A layout evaluation method is based on the analysis of an activity graph derived from a circuit layout. The cost measure for such a graph is defined and used in evaluation of the necessary and sufficient conditions for design optimality (NSCDO). Iterations within the optimization process are controlled using a synthetic measure derived from these optimality conditions. A proposed layout optimization heuristic, derived from NSCDO, allows for better routing channel area utilization without compromising a circuit's timing performance. It is based on an analysis of the timing behavior modifications introduced by the various materials used as interconnectors resulting in an improvement of the load dependency of the output driving capabilities of cells. The dissertation contains an example of a quantitative analysis of a CMOS digital circuit. A system implementing some of the algorithms described above has been written in FORTRAN77.
Type:
text; Dissertation-Reproduction (electronic)
Keywords:
Computer architecture.; Digital electronics.
Degree Name:
Ph.D.
Degree Level:
doctoral
Degree Program:
Electrical and Computer Engineering; Graduate College
Degree Grantor:
University of Arizona

Full metadata record

DC FieldValue Language
dc.language.isoenen_US
dc.titleAN OPTIMIZATION STAGE FOR AHPL COMPILER (LAYOUT).en_US
dc.creatorMAITAN, JACEK.en_US
dc.contributor.authorMAITAN, JACEK.en_US
dc.date.issued1984en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractThe dissertation is a description of an analysis and a case study of an Optimization Stage for a Standard Cell oriented silicon compiler. Using the AHPL hardware description language, a complete representation hierarchy (functional, logic, and layout) is proposed for circuits defined at a Register Transfer level. The design of a new class of methods for layout analysis and optimization is based on this hierarchy. A layout evaluation method is based on the analysis of an activity graph derived from a circuit layout. The cost measure for such a graph is defined and used in evaluation of the necessary and sufficient conditions for design optimality (NSCDO). Iterations within the optimization process are controlled using a synthetic measure derived from these optimality conditions. A proposed layout optimization heuristic, derived from NSCDO, allows for better routing channel area utilization without compromising a circuit's timing performance. It is based on an analysis of the timing behavior modifications introduced by the various materials used as interconnectors resulting in an improvement of the load dependency of the output driving capabilities of cells. The dissertation contains an example of a quantitative analysis of a CMOS digital circuit. A system implementing some of the algorithms described above has been written in FORTRAN77.en_US
dc.typetexten_US
dc.typeDissertation-Reproduction (electronic)en_US
dc.subjectComputer architecture.en_US
dc.subjectDigital electronics.en_US
thesis.degree.namePh.D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.identifier.proquest8415074en_US
dc.identifier.oclc691272142en_US
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