Persistent Link:
http://hdl.handle.net/10150/186986
Title:
Structuring VHDL synthesis using the AHPL paradigm.
Author:
Massoumi, Mehran Mokhtar.
Issue Date:
1994
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
The widespread use of VHDL for RT synthesis in the design community and the problems associated with using the language for such a purpose is the driving force behind defining this research. Although VHDL includes constructs that can be useful in design representation, it will be demonstrated that synthesis from VHDL does not produce optimum results and is not computationally efficient. A number of real design scenarios will be analyzed and the pitfalls associated with each will be highlighted. The alternative is to use a language that is designed for synthesis and yet possesses all the representation power of VHDL. AHPL (A Hardware Programming Language) will be used for this purpose. Due to the one to one correspondence between AHPL constructs and the hardware primitives, derivation of hardware from the description is a natural process. Although AHPL has proved to be a robust and effective synthesis language, it requires modest extensions so that all models described in VHDL synthesis subsets can also be described in AHPL at the same level of abstraction as VHDL. The resulting language will be referred to as Extended AHPL or XAHPL for short. A synthesis methodology and implementation using XAHPL will be presented. Moreover, the results of synthesizing XAHPL and equivalent VHDL models under the same constraints and environment will be compared. This comparison can be interpreted as a cost metric for the VHDL synthesis methodology. Lastly, since many designers are and will be using VHDL for synthesis, a subset of VHDL which carries most correspondence with XAHPL will be defined.
Type:
text; Dissertation-Reproduction (electronic)
Degree Name:
Ph.D.
Degree Level:
doctoral
Degree Program:
Electrical and Computer Engineering; Graduate College
Degree Grantor:
University of Arizona
Committee Chair:
Hill, Frederick J.

Full metadata record

DC FieldValue Language
dc.language.isoenen_US
dc.titleStructuring VHDL synthesis using the AHPL paradigm.en_US
dc.creatorMassoumi, Mehran Mokhtar.en_US
dc.contributor.authorMassoumi, Mehran Mokhtar.en_US
dc.date.issued1994en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractThe widespread use of VHDL for RT synthesis in the design community and the problems associated with using the language for such a purpose is the driving force behind defining this research. Although VHDL includes constructs that can be useful in design representation, it will be demonstrated that synthesis from VHDL does not produce optimum results and is not computationally efficient. A number of real design scenarios will be analyzed and the pitfalls associated with each will be highlighted. The alternative is to use a language that is designed for synthesis and yet possesses all the representation power of VHDL. AHPL (A Hardware Programming Language) will be used for this purpose. Due to the one to one correspondence between AHPL constructs and the hardware primitives, derivation of hardware from the description is a natural process. Although AHPL has proved to be a robust and effective synthesis language, it requires modest extensions so that all models described in VHDL synthesis subsets can also be described in AHPL at the same level of abstraction as VHDL. The resulting language will be referred to as Extended AHPL or XAHPL for short. A synthesis methodology and implementation using XAHPL will be presented. Moreover, the results of synthesizing XAHPL and equivalent VHDL models under the same constraints and environment will be compared. This comparison can be interpreted as a cost metric for the VHDL synthesis methodology. Lastly, since many designers are and will be using VHDL for synthesis, a subset of VHDL which carries most correspondence with XAHPL will be defined.en_US
dc.typetexten_US
dc.typeDissertation-Reproduction (electronic)en_US
thesis.degree.namePh.D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.chairHill, Frederick J.en_US
dc.contributor.committeememberZeigler, Bernarden_US
dc.contributor.committeememberCarothers, Jo Daleen_US
dc.identifier.proquest9517596en_US
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