Performance and area optimization in sea-of-wires array synthesis.

Persistent Link:
http://hdl.handle.net/10150/186766
Title:
Performance and area optimization in sea-of-wires array synthesis.
Author:
Chen, Geng-lin.
Issue Date:
1994
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
This dissertation addresses several techniques used for the layout optimization with respect to both delay and chip area of the Sea-of-Wires Array, a unique CMOS design methodology. SWAPSS, Sea-of-Wires Array Performance Sensitive Synthesis, is an automated design tool that maps the input RIF (RTL Intermediate Formate) specification onto the output SLF (Symbolic Layout Format) of Sea-of-Wires Array. The work described in the dissertation can be divided into four parts. The first part describes the improvement in the placement and interconnection of synthesis from previous work. The second part introduces techniques used for area optimization. Those techniques include logic simplification, gate re-ordering, column folding and row folding. The third part describes techniques like transistors sizing, buffer inserting and gate breaking that are used for performance optimization. A two-table delay approximation is used to facilitate a fast and accurate timing analysis. The avoiding of false paths introduced from control part of the design is done by passing the design information from high level (Register Transfer Level) to the timing analysis in the layout level. The results of several benchmarks are given in the last part of the dissertation. By comparing SWAPSS with other design methods, it shows that results from SWAPSS have better performance in most of the benchmark circuits.
Type:
text; Dissertation-Reproduction (electronic)
Degree Name:
Ph.D.
Degree Level:
doctoral
Degree Program:
Electrical and Computer Engineering; Graduate College
Degree Grantor:
University of Arizona
Committee Chair:
Hill, Fredrick J.

Full metadata record

DC FieldValue Language
dc.language.isoenen_US
dc.titlePerformance and area optimization in sea-of-wires array synthesis.en_US
dc.creatorChen, Geng-lin.en_US
dc.contributor.authorChen, Geng-lin.en_US
dc.date.issued1994en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractThis dissertation addresses several techniques used for the layout optimization with respect to both delay and chip area of the Sea-of-Wires Array, a unique CMOS design methodology. SWAPSS, Sea-of-Wires Array Performance Sensitive Synthesis, is an automated design tool that maps the input RIF (RTL Intermediate Formate) specification onto the output SLF (Symbolic Layout Format) of Sea-of-Wires Array. The work described in the dissertation can be divided into four parts. The first part describes the improvement in the placement and interconnection of synthesis from previous work. The second part introduces techniques used for area optimization. Those techniques include logic simplification, gate re-ordering, column folding and row folding. The third part describes techniques like transistors sizing, buffer inserting and gate breaking that are used for performance optimization. A two-table delay approximation is used to facilitate a fast and accurate timing analysis. The avoiding of false paths introduced from control part of the design is done by passing the design information from high level (Register Transfer Level) to the timing analysis in the layout level. The results of several benchmarks are given in the last part of the dissertation. By comparing SWAPSS with other design methods, it shows that results from SWAPSS have better performance in most of the benchmark circuits.en_US
dc.typetexten_US
dc.typeDissertation-Reproduction (electronic)en_US
thesis.degree.namePh.D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.chairHill, Fredrick J.en_US
dc.contributor.committeememberCarothers, Jo Daleen_US
dc.contributor.committeememberVrudhula, Sarma B. K.en_US
dc.identifier.proquest9432836en_US
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