Characterization and modeling of high speed, high resolution focal plane arrays.

Persistent Link:
http://hdl.handle.net/10150/186737
Title:
Characterization and modeling of high speed, high resolution focal plane arrays.
Author:
Graeve, Thorsten.
Issue Date:
1994
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
The work presented in this dissertation examines the characterization and modeling of visible charge-coupled devices (CCDs). A theoretical model is discussed that represents the parallel clock register of a CCD as a lumped system of discrete resistances and capacitances. This model can be used to simulate the electrical performance of the clock register. From the simulation results the clock pulse degradation in the lossy transmission line model of the clock electrode can be determined. An upper limit is found to the parallel clock frequency at which reasonable pulse shapes are preserved. In addition, the model is used to find the current flow and the power dissipation within the clock electrodes. Through simulations, the total power dissipation on a high-speed, high-resolution CCD can be calculated and compared to theoretical values obtained from a conventional model. The experimental part of this dissertation covers the theory and application of test methodology for the characterization of high-speed, high-resolution CCDs. Both standard and novel techniques for CCD evaluation are discussed, covering all standard figures-of-merit such as read noise, full-well capacity, dynamic range, conversion gain, charge transfer efficiency, MTF, quantum efficiency, non-uniformity, dark current, linearity and lag. This chapter is followed by a discussion of the test camera hardware and software that is used to develop characterization techniques and apply them to specific devices. Finally, the characterization results from applying these techniques to the English Electric Valve (EEV) CCD13 are presented. This device is a 512 by 512 pixel, 8-output, three-phase, full-frame CCD that was designed for readout periods of less than 2 ms. It has been characterized at data rates up to 1 MHz, resulting in video acquisition of 128 by 64 pixel subarrays at 100 frames per second. The results show that both experimental characterization and theoretical modeling are two important aspects of CCD evaluation, providing necessary data to customers and valuable feedback to manufacturers.
Type:
text; Dissertation-Reproduction (electronic)
Degree Name:
Ph.D.
Degree Level:
doctoral
Degree Program:
Optical Sciences; Graduate College
Degree Grantor:
University of Arizona
Committee Chair:
Dereniak, Eustace L.

Full metadata record

DC FieldValue Language
dc.language.isoenen_US
dc.titleCharacterization and modeling of high speed, high resolution focal plane arrays.en_US
dc.creatorGraeve, Thorsten.en_US
dc.contributor.authorGraeve, Thorsten.en_US
dc.date.issued1994en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractThe work presented in this dissertation examines the characterization and modeling of visible charge-coupled devices (CCDs). A theoretical model is discussed that represents the parallel clock register of a CCD as a lumped system of discrete resistances and capacitances. This model can be used to simulate the electrical performance of the clock register. From the simulation results the clock pulse degradation in the lossy transmission line model of the clock electrode can be determined. An upper limit is found to the parallel clock frequency at which reasonable pulse shapes are preserved. In addition, the model is used to find the current flow and the power dissipation within the clock electrodes. Through simulations, the total power dissipation on a high-speed, high-resolution CCD can be calculated and compared to theoretical values obtained from a conventional model. The experimental part of this dissertation covers the theory and application of test methodology for the characterization of high-speed, high-resolution CCDs. Both standard and novel techniques for CCD evaluation are discussed, covering all standard figures-of-merit such as read noise, full-well capacity, dynamic range, conversion gain, charge transfer efficiency, MTF, quantum efficiency, non-uniformity, dark current, linearity and lag. This chapter is followed by a discussion of the test camera hardware and software that is used to develop characterization techniques and apply them to specific devices. Finally, the characterization results from applying these techniques to the English Electric Valve (EEV) CCD13 are presented. This device is a 512 by 512 pixel, 8-output, three-phase, full-frame CCD that was designed for readout periods of less than 2 ms. It has been characterized at data rates up to 1 MHz, resulting in video acquisition of 128 by 64 pixel subarrays at 100 frames per second. The results show that both experimental characterization and theoretical modeling are two important aspects of CCD evaluation, providing necessary data to customers and valuable feedback to manufacturers.en_US
dc.typetexten_US
dc.typeDissertation-Reproduction (electronic)en_US
thesis.degree.namePh.D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineOptical Sciencesen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.chairDereniak, Eustace L.en_US
dc.contributor.committeememberSlater, Philip N.en_US
dc.contributor.committeememberMcCurnin, Thomas W.en_US
dc.identifier.proquest9426565en_US
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