A high-frequency integrated CMOS phase-locked loop independent of silicon process variations and temperature conditions.

Persistent Link:
http://hdl.handle.net/10150/186575
Title:
A high-frequency integrated CMOS phase-locked loop independent of silicon process variations and temperature conditions.
Author:
Atriss, Ahmad Hussein.
Issue Date:
1993
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
The increasing demand for local high-frequency operations on microprocessor and data-communication chips has led to the need for phase-locked loops to generate on-chip high-frequency clocks controlled by a much lower-frequency externally-provided system reference clocks. A high-frequency integrated CMOS phase-locked loop, which is independent of temperature and silicon processing variations, has been designed and tested. The system-level design was based on both frequency linear analysis and transient time-domain analysis performed using MTIME simulations. The design in this work integrates a phase-frequency detector, a symmetric charge-pump, an external low-pass RC loop filter, a digital-load-controlled voltage-controlled oscillator (DLCVCO), a programmable feedback-divider, a frequency-range detector (FRD), a circuit which initializes the loop filter node to VDD, a digital-load-activation cell, and associated circuitry on a portion of one die. The DLCVCO was implemented by a ring of three inverters; frequency was controlled by digitally programming the capacitive loads connected to its inner nodes. The FRD was designed to sense the temperature and silicon process conditions of the PLL system, and control the number of capacitive loads activated to the inner nodes of the DLCVCO. A 0.8 μm CMOS process was used to implement this PLL system design. Tests demonstrated that this PLL generated frequencies in excess of 200MHz, locked onto a 2MHz reference clock, and achieved a tuning range of 12MHz to 212MHz independent of silicon process variations and temperature conditions.
Type:
text; Dissertation-Reproduction (electronic)
Keywords:
Electrical engineering.
Degree Name:
Ph.D.
Degree Level:
doctoral
Degree Program:
Electrical and Computer Engineering; Graduate College
Degree Grantor:
University of Arizona
Committee Chair:
Gerhard, Glen C.

Full metadata record

DC FieldValue Language
dc.language.isoenen_US
dc.titleA high-frequency integrated CMOS phase-locked loop independent of silicon process variations and temperature conditions.en_US
dc.creatorAtriss, Ahmad Hussein.en_US
dc.contributor.authorAtriss, Ahmad Hussein.en_US
dc.date.issued1993en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractThe increasing demand for local high-frequency operations on microprocessor and data-communication chips has led to the need for phase-locked loops to generate on-chip high-frequency clocks controlled by a much lower-frequency externally-provided system reference clocks. A high-frequency integrated CMOS phase-locked loop, which is independent of temperature and silicon processing variations, has been designed and tested. The system-level design was based on both frequency linear analysis and transient time-domain analysis performed using MTIME simulations. The design in this work integrates a phase-frequency detector, a symmetric charge-pump, an external low-pass RC loop filter, a digital-load-controlled voltage-controlled oscillator (DLCVCO), a programmable feedback-divider, a frequency-range detector (FRD), a circuit which initializes the loop filter node to VDD, a digital-load-activation cell, and associated circuitry on a portion of one die. The DLCVCO was implemented by a ring of three inverters; frequency was controlled by digitally programming the capacitive loads connected to its inner nodes. The FRD was designed to sense the temperature and silicon process conditions of the PLL system, and control the number of capacitive loads activated to the inner nodes of the DLCVCO. A 0.8 μm CMOS process was used to implement this PLL system design. Tests demonstrated that this PLL generated frequencies in excess of 200MHz, locked onto a 2MHz reference clock, and achieved a tuning range of 12MHz to 212MHz independent of silicon process variations and temperature conditions.en_US
dc.typetexten_US
dc.typeDissertation-Reproduction (electronic)en_US
dc.subjectElectrical engineering.en_US
thesis.degree.namePh.D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.chairGerhard, Glen C.en_US
dc.contributor.committeememberWait, John V.en_US
dc.contributor.committeememberWitulski, Arthur F.en_US
dc.contributor.committeememberBrillhart, John D.en_US
dc.contributor.committeememberMoloney, Jerry V.en_US
dc.identifier.proquest9421780en_US
dc.identifier.oclc702682543en_US
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