A computer-aided design framework for modeling and simulation of VLSI interconnects.

Persistent Link:
http://hdl.handle.net/10150/186363
Title:
A computer-aided design framework for modeling and simulation of VLSI interconnects.
Author:
Hsu, Pochang.
Issue Date:
1993
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
The rising complexity of interconnect and packaging structures in VLSI systems has increased the necessity of applying modeling and simulation techniques for analysis and design. To effectively manage design data and CAD tools for modeling and simulations of electronic packaging, a framework which provides different levels of services is essential. This paper discusses a computer-aided design framework for the aforementioned purposes. A CAD framework with a five layered architecture is developed to support the analysis and design for VLSI packaging and interconnects. The first layer of the framework emphasizes the fundamental integration of CAD tools and simulation management. In the second layer of the architecture, design data representation and management are stressed. Two design databases termed the Chip Model Library and the Packaging Model Library are developed and coupled in this layer. We applied an object-oriented approach to implement libraries and encapsulate CAD tools. System level (board level) modeling and simulation are presented in the third layer of the framework. CMOS based multichip modules (MCMs) are used for our discussion. The fourth layer is for the automation of design process by coordinating different CAD tools. The highest layer in the proposed CAD framework is the level for design methodology management. A rule and frame based system is illustrated for simulation model generation of electronic packages.
Type:
text; Dissertation-Reproduction (electronic)
Keywords:
Dissertations, Academic.; Electrical engineering.
Degree Name:
Ph.D.
Degree Level:
doctoral
Degree Program:
Electrical and Computer Engineering; Graduate College
Degree Grantor:
University of Arizona
Committee Chair:
Rozenblit, Jerzy W.

Full metadata record

DC FieldValue Language
dc.language.isoenen_US
dc.titleA computer-aided design framework for modeling and simulation of VLSI interconnects.en_US
dc.creatorHsu, Pochang.en_US
dc.contributor.authorHsu, Pochang.en_US
dc.date.issued1993en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractThe rising complexity of interconnect and packaging structures in VLSI systems has increased the necessity of applying modeling and simulation techniques for analysis and design. To effectively manage design data and CAD tools for modeling and simulations of electronic packaging, a framework which provides different levels of services is essential. This paper discusses a computer-aided design framework for the aforementioned purposes. A CAD framework with a five layered architecture is developed to support the analysis and design for VLSI packaging and interconnects. The first layer of the framework emphasizes the fundamental integration of CAD tools and simulation management. In the second layer of the architecture, design data representation and management are stressed. Two design databases termed the Chip Model Library and the Packaging Model Library are developed and coupled in this layer. We applied an object-oriented approach to implement libraries and encapsulate CAD tools. System level (board level) modeling and simulation are presented in the third layer of the framework. CMOS based multichip modules (MCMs) are used for our discussion. The fourth layer is for the automation of design process by coordinating different CAD tools. The highest layer in the proposed CAD framework is the level for design methodology management. A rule and frame based system is illustrated for simulation model generation of electronic packages.en_US
dc.typetexten_US
dc.typeDissertation-Reproduction (electronic)en_US
dc.subjectDissertations, Academic.en_US
dc.subjectElectrical engineering.en_US
thesis.degree.namePh.D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.chairRozenblit, Jerzy W.en_US
dc.contributor.committeememberPrince, John L.en_US
dc.contributor.committeememberHill, Frederick J.en_US
dc.identifier.proquest9408395en_US
dc.identifier.oclc720402560en_US
All Items in UA Campus Repository are protected by copyright, with all rights reserved, unless otherwise indicated.