Persistent Link:
http://hdl.handle.net/10150/186020
Title:
Synthesis of VLSI sea-of-wires arrays.
Author:
Chen, Ing-Yi.
Issue Date:
1992
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
The primary intent of this dissertation project has been to assess the potential of a unique CMOS design capability, which is derived from a methodology known as Sea-of-Wires Arrays (SWA). The new capability is expected to yield the performance benefits of a custom design while maintaining the quick turnaround and ease of semicustom design for ASIC applications. The specific goal of this research is to develop the design representations, design techniques, and computer software for the SWA design methodology. This includes the design and analysis of heuristic algorithms for every issue related to synthesis, logic minimization and layout optimization with respect to both delay and chip area. The research begins by showing that the SWA architecture based on distributed gates is a promising approach to VLSI design. The synthesis and optimization algorithms form the core of the design system whose goal is high-performance SWA design. The innovative table lookup timing analysis approach facilitates a fast and accurate performance evaluation. Numerous programs have been written to constitute the performance-driven SWA synthesis system that maps the input RIF (RTL Intermediate Format) specification onto the output SLF (Symbolic Layout Format) layout with satisfaction of constraints dictated by technology, design flow, and manufacturability. This is based on a well-designed Data Modeler which specifies both RIF and SLF design representations. The present results, obtained from a number of benchmark designs, indicate that the research goals have been fulfilled. Fast turn-around time and a density advantage make the SWA approach a potentially important player in the commercial market. However, the research project presented here is not yet the final solution. The ultimate goal of future research is to achieve an SWA chip layout that compares favorably with manual design of the same architecture.
Type:
text; Dissertation-Reproduction (electronic)
Keywords:
Dissertations, Academic.; Electrical engineering.
Degree Name:
Ph.D.
Degree Level:
doctoral
Degree Program:
Electrical and Computer Engineering; Graduate College
Degree Grantor:
University of Arizona
Committee Chair:
Hill, Fredrick J.

Full metadata record

DC FieldValue Language
dc.language.isoenen_US
dc.titleSynthesis of VLSI sea-of-wires arrays.en_US
dc.creatorChen, Ing-Yi.en_US
dc.contributor.authorChen, Ing-Yi.en_US
dc.date.issued1992en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractThe primary intent of this dissertation project has been to assess the potential of a unique CMOS design capability, which is derived from a methodology known as Sea-of-Wires Arrays (SWA). The new capability is expected to yield the performance benefits of a custom design while maintaining the quick turnaround and ease of semicustom design for ASIC applications. The specific goal of this research is to develop the design representations, design techniques, and computer software for the SWA design methodology. This includes the design and analysis of heuristic algorithms for every issue related to synthesis, logic minimization and layout optimization with respect to both delay and chip area. The research begins by showing that the SWA architecture based on distributed gates is a promising approach to VLSI design. The synthesis and optimization algorithms form the core of the design system whose goal is high-performance SWA design. The innovative table lookup timing analysis approach facilitates a fast and accurate performance evaluation. Numerous programs have been written to constitute the performance-driven SWA synthesis system that maps the input RIF (RTL Intermediate Format) specification onto the output SLF (Symbolic Layout Format) layout with satisfaction of constraints dictated by technology, design flow, and manufacturability. This is based on a well-designed Data Modeler which specifies both RIF and SLF design representations. The present results, obtained from a number of benchmark designs, indicate that the research goals have been fulfilled. Fast turn-around time and a density advantage make the SWA approach a potentially important player in the commercial market. However, the research project presented here is not yet the final solution. The ultimate goal of future research is to achieve an SWA chip layout that compares favorably with manual design of the same architecture.en_US
dc.typetexten_US
dc.typeDissertation-Reproduction (electronic)en_US
dc.subjectDissertations, Academic.en_US
dc.subjectElectrical engineering.en_US
thesis.degree.namePh.D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.chairHill, Fredrick J.en_US
dc.contributor.committeememberRozenblit, Jerzy W.en_US
dc.contributor.committeememberCarothers, Jo Daleen_US
dc.identifier.proquest9307680en_US
dc.identifier.oclc713919351en_US
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