High yield and reliable sorting networks for VLSI and WSI implementations.

Persistent Link:
http://hdl.handle.net/10150/185520
Title:
High yield and reliable sorting networks for VLSI and WSI implementations.
Author:
Liang, Sheng-Chiech.
Issue Date:
1991
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
In this dissertation, a novel approach to on-line error detection and correction for high throughput VLSI sorting arrays is presented first. Two-level pipelining is employed in the design which makes the proposed VLSI sorting array very efficient and suitable for real-time applications. All the checkers are designed as totally self-checking circuits such that the resulting sorting array is extremely reliable. Next, in order to overcome the yield problem in WSI implementations a novel hierarchical modular sorting network is presented. More regularly structured equivalent sorting networks are introduced by replacing shuffle interconnections in the original sorting network with easily reconfigurable interconnections. Redundancy is provided at every level of the hierarchy. Hierarchical reconfiguration is implemented by replacing the defective cells with spare cells at the bottom level first, and goes to the next higher level. Yield analysis is performed to demonstrate the effectiveness of our approach. Efficient implementation of parallel sorting algorithms for mesh-connected processor arrays are also considered in this dissertation. The trapezoid sort which has the properties of very simple control hardware and ease of implementation for mesh-connected processor arrays is developed. Its advantage is that the number of iterations is improved significantly compared with the existing parallel sorting algorithms on mesh-connected processor arrays. Based on this algorithm, an efficient method is proposed to find the median value of the input elements. The elements outside the boundary are excluded from the remaining sorting process to reduce the time complexity. This method is then extended to finding the kth smallest element in the input array. Finally, if the number of elements to be sorted is larger than N, the trapezoid sort algorithm can not be applied directly. Therefore, a modified odd-even merge procedure is presented to merge m sorted input sets. The modified odd-even merge procedure can sort two sets of data inputs concurrently by utilizing the idle processors and then merge them together. A speedup of O(log₂m) over the previous merge-split method is achieved.
Type:
text; Dissertation-Reproduction (electronic)
Keywords:
Dissertations, Academic; Computer science.
Degree Name:
Ph.D.
Degree Level:
doctoral
Degree Program:
Electrical, and Computer Engineering; Graduate College
Degree Grantor:
University of Arizona
Advisor:
Kuo, Sy-Yen

Full metadata record

DC FieldValue Language
dc.language.isoenen_US
dc.titleHigh yield and reliable sorting networks for VLSI and WSI implementations.en_US
dc.creatorLiang, Sheng-Chiech.en_US
dc.contributor.authorLiang, Sheng-Chiech.en_US
dc.date.issued1991en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractIn this dissertation, a novel approach to on-line error detection and correction for high throughput VLSI sorting arrays is presented first. Two-level pipelining is employed in the design which makes the proposed VLSI sorting array very efficient and suitable for real-time applications. All the checkers are designed as totally self-checking circuits such that the resulting sorting array is extremely reliable. Next, in order to overcome the yield problem in WSI implementations a novel hierarchical modular sorting network is presented. More regularly structured equivalent sorting networks are introduced by replacing shuffle interconnections in the original sorting network with easily reconfigurable interconnections. Redundancy is provided at every level of the hierarchy. Hierarchical reconfiguration is implemented by replacing the defective cells with spare cells at the bottom level first, and goes to the next higher level. Yield analysis is performed to demonstrate the effectiveness of our approach. Efficient implementation of parallel sorting algorithms for mesh-connected processor arrays are also considered in this dissertation. The trapezoid sort which has the properties of very simple control hardware and ease of implementation for mesh-connected processor arrays is developed. Its advantage is that the number of iterations is improved significantly compared with the existing parallel sorting algorithms on mesh-connected processor arrays. Based on this algorithm, an efficient method is proposed to find the median value of the input elements. The elements outside the boundary are excluded from the remaining sorting process to reduce the time complexity. This method is then extended to finding the kth smallest element in the input array. Finally, if the number of elements to be sorted is larger than N, the trapezoid sort algorithm can not be applied directly. Therefore, a modified odd-even merge procedure is presented to merge m sorted input sets. The modified odd-even merge procedure can sort two sets of data inputs concurrently by utilizing the idle processors and then merge them together. A speedup of O(log₂m) over the previous merge-split method is achieved.en_US
dc.typetexten_US
dc.typeDissertation-Reproduction (electronic)en_US
dc.subjectDissertations, Academicen_US
dc.subjectComputer science.en_US
thesis.degree.namePh.D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineElectrical, and Computer Engineeringen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorKuo, Sy-Yenen_US
dc.contributor.committeememberLouri, Ahmeden_US
dc.contributor.committeememberHill, Fredrick J.en_US
dc.identifier.proquest9136851en_US
dc.identifier.oclc710854608en_US
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