Fault diagnosis and yield enhancement in defect-tolerant VLSI/WSI parallel architectures.

Persistent Link:
http://hdl.handle.net/10150/185414
Title:
Fault diagnosis and yield enhancement in defect-tolerant VLSI/WSI parallel architectures.
Author:
Wang, Kuochen.
Issue Date:
1991
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
This dissertation presents an integrated high-level computer-aided design (CAD) environment, the VAR (VHDL-based Array Reconfiguration) system, for the tasks of design, diagnosis, reconfiguration, simulation, and evaluation in a defect tolerant VLSI/WSI (Wafer Scale Integration) parallel architecture modeled by VHDL. Four issues in the VAR system are studied: (1) the development of a CAD framework for reconfigurable architectures, (2) the development of an array model, and its VHDL description and simulation, (3) the development of efficient fault diagnosis techniques, and (4) the development of a systematic method for evaluating architectures and yield. The first issue describes the modules in the CAD framework and their functionalities. The second issue addresses the hierarchical VHDL description and simulation of the array model, and the detailed designs of its components. The third issue proposes two fault diagnosis algorithms based on the parallel partition approach and the self-comparison approach respectively, and an optimal group diagnosis procedure. These fault diagnosis techniques all have the contribution of reducing testing time significantly under different application scenarios. The fourth issue depicts a complete set of figures of merits for quantitative architecture and yield evaluation. Although an easily diagnosable and reconfigurable two-dimensional defect tolerant array is used as an example to illustrate the methodology of VAR, the VAR environment can be equally applied to other parallel architectures. VAR allows the designers to study and evaluate fault diagnosis and reconfiguration algorithms by inserting faults, which are generated according to actual manufacturing yield data, into the array and then locating the faulty elements as well as simulating the reconfiguration process. Thus, VAR can assist the designers in evaluating different combinations of fault patterns, fault diagnosis and reconfiguration techniques, and reconfigurable architectures through the figures of merit with aim at architectural improvements. Extensive simulation and evaluation have been performed to demonstrate and support the effectiveness of VAR. The results from this research can drive the applications of large area VLSI or WSI closer to reality and result in producing low cost and high yield parallel architectures.
Type:
text; Dissertation-Reproduction (electronic)
Keywords:
Algorithms and architectures for advanced scientific computing
Degree Name:
Ph.D.
Degree Level:
doctoral
Degree Program:
Electrical and Computer Engineering; Graduate College
Degree Grantor:
University of Arizona
Advisor:
Kuo, Sy-Yen

Full metadata record

DC FieldValue Language
dc.language.isoenen_US
dc.titleFault diagnosis and yield enhancement in defect-tolerant VLSI/WSI parallel architectures.en_US
dc.creatorWang, Kuochen.en_US
dc.contributor.authorWang, Kuochen.en_US
dc.date.issued1991en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractThis dissertation presents an integrated high-level computer-aided design (CAD) environment, the VAR (VHDL-based Array Reconfiguration) system, for the tasks of design, diagnosis, reconfiguration, simulation, and evaluation in a defect tolerant VLSI/WSI (Wafer Scale Integration) parallel architecture modeled by VHDL. Four issues in the VAR system are studied: (1) the development of a CAD framework for reconfigurable architectures, (2) the development of an array model, and its VHDL description and simulation, (3) the development of efficient fault diagnosis techniques, and (4) the development of a systematic method for evaluating architectures and yield. The first issue describes the modules in the CAD framework and their functionalities. The second issue addresses the hierarchical VHDL description and simulation of the array model, and the detailed designs of its components. The third issue proposes two fault diagnosis algorithms based on the parallel partition approach and the self-comparison approach respectively, and an optimal group diagnosis procedure. These fault diagnosis techniques all have the contribution of reducing testing time significantly under different application scenarios. The fourth issue depicts a complete set of figures of merits for quantitative architecture and yield evaluation. Although an easily diagnosable and reconfigurable two-dimensional defect tolerant array is used as an example to illustrate the methodology of VAR, the VAR environment can be equally applied to other parallel architectures. VAR allows the designers to study and evaluate fault diagnosis and reconfiguration algorithms by inserting faults, which are generated according to actual manufacturing yield data, into the array and then locating the faulty elements as well as simulating the reconfiguration process. Thus, VAR can assist the designers in evaluating different combinations of fault patterns, fault diagnosis and reconfiguration techniques, and reconfigurable architectures through the figures of merit with aim at architectural improvements. Extensive simulation and evaluation have been performed to demonstrate and support the effectiveness of VAR. The results from this research can drive the applications of large area VLSI or WSI closer to reality and result in producing low cost and high yield parallel architectures.en_US
dc.typetexten_US
dc.typeDissertation-Reproduction (electronic)en_US
dc.subjectAlgorithms and architectures for advanced scientific computingen_US
thesis.degree.namePh.D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorKuo, Sy-Yenen_US
dc.contributor.committeememberHill, Frederick J.en_US
dc.contributor.committeememberRozenblit, Jerzy W.en_US
dc.identifier.proquest9123467en_US
dc.identifier.oclc702670015en_US
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