Persistent Link:
http://hdl.handle.net/10150/185071
Title:
VLSI REALIZATION OF AHPL DESCRIPTIONS AS STORAGE LOGIC ARRAY.
Author:
CHIANG, CHEN HUEI.
Issue Date:
1982
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
A methodology for the automatic translation of a Hardware Description Language (HDL) formulation of a VLSI system to a structured array-type of target realization is the subject of this investigation. A particular combination of input HDL and target technology has been implemented as part of the exercise, and a detailed evaluation of the result is presented. The HDL used in the study is AHPL, a synchronous clock-mode language which accepts the description of the hardware at Register Transfer Level. The target technology selected is Storage Logic Array (SLA), an evolution of PLA concept. Use of the SLA has a distinct advantage, notably in the ability to sidestep the interconnection routing problem, an expensive and time-consuming process in normal IC design. Over the past years, an enormous amount of effort has gone into generation of layout from an interconnection list. This conventional approach seems to complicate the placement and routing processes in later stages. In this research project the major emphasis has therefore been on extracting relevant global information from the higher-level description to guide the subsequent placement and routing algorithms. This effectively generates the lower-level layout directly from higher-level description. A special version of AHPL compiler (stage 3) has been developed as part of the project. The SLA data structure formats and the implementation of the Data and Control Sections of the target are described in detail. Also the evaluation and possibilities for future research are discussed.
Type:
text; Dissertation-Reproduction (electronic)
Keywords:
Integrated circuits -- Very large scale integration -- Design.; APL (Computer program language); Engineering design -- Automation.
Degree Name:
Ph.D.
Degree Level:
doctoral
Degree Program:
Electrical Engineering; Graduate College
Degree Grantor:
University of Arizona

Full metadata record

DC FieldValue Language
dc.language.isoenen_US
dc.titleVLSI REALIZATION OF AHPL DESCRIPTIONS AS STORAGE LOGIC ARRAY.en_US
dc.creatorCHIANG, CHEN HUEI.en_US
dc.contributor.authorCHIANG, CHEN HUEI.en_US
dc.date.issued1982en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractA methodology for the automatic translation of a Hardware Description Language (HDL) formulation of a VLSI system to a structured array-type of target realization is the subject of this investigation. A particular combination of input HDL and target technology has been implemented as part of the exercise, and a detailed evaluation of the result is presented. The HDL used in the study is AHPL, a synchronous clock-mode language which accepts the description of the hardware at Register Transfer Level. The target technology selected is Storage Logic Array (SLA), an evolution of PLA concept. Use of the SLA has a distinct advantage, notably in the ability to sidestep the interconnection routing problem, an expensive and time-consuming process in normal IC design. Over the past years, an enormous amount of effort has gone into generation of layout from an interconnection list. This conventional approach seems to complicate the placement and routing processes in later stages. In this research project the major emphasis has therefore been on extracting relevant global information from the higher-level description to guide the subsequent placement and routing algorithms. This effectively generates the lower-level layout directly from higher-level description. A special version of AHPL compiler (stage 3) has been developed as part of the project. The SLA data structure formats and the implementation of the Data and Control Sections of the target are described in detail. Also the evaluation and possibilities for future research are discussed.en_US
dc.typetexten_US
dc.typeDissertation-Reproduction (electronic)en_US
dc.subjectIntegrated circuits -- Very large scale integration -- Design.en_US
dc.subjectAPL (Computer program language)en_US
dc.subjectEngineering design -- Automation.en_US
thesis.degree.namePh.D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineElectrical Engineeringen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.identifier.proquest8305975en_US
dc.identifier.oclc686764177en_US
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