An intelligent function level backward state justification search for ATPG.

Persistent Link:
http://hdl.handle.net/10150/184921
Title:
An intelligent function level backward state justification search for ATPG.
Author:
Karunaratne, Maddumage Don Gamini.
Issue Date:
1989
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
This dissertation describes an innovative approach to the state justification portion of the sequential circuit automatic test pattern generation (ATPG) process. Given the absence of a stored fault an ATPG controller invokes some combinational circuit test generation procedure, such as the D-algorithm, to identify a circuit state (goal state) and input vectors that will sensitize a selected fault. The state justification phase then finds a transfer sequence to the goal from the present state. A forward fault propogation search can be successfully guided through state space from the present state but the forward justification search is less efficient and the failure rate is high. The backward function level search invokes inverse RTL level primitives and exploits easy movement of data vectors in structured VLSI circuits. Examples illustrated are in AHPL. This search is equally applicable to an RTL level subset of VHDL. Combinational logic units are treated as functions and the circuit states are partitioned into control states and data states. The search proceeds backwards over the control state space starting from the goal state node and data states are transformed according to the control flow. Vectorized data paths in VLSI circuits and search guiding heuristics which favor convenient inverse functions keep the number of search nodes low. Partial covers, conceptually similar to singular covers in D-algorithm, model the inverse functions of combinational logic units. The search successfully terminates when a child state node logically matches the present state and the present state values can satisfy all the constraints encountered along the search path.
Type:
text; Dissertation-Reproduction (electronic)
Keywords:
Integrated circuits -- Very large scale integration -- Testing; Electric circuits -- Testing
Degree Name:
Ph.D.
Degree Level:
doctoral
Degree Program:
Electrical and Computer Engineering; Graduate College
Degree Grantor:
University of Arizona
Advisor:
Hill, Fredrick J.

Full metadata record

DC FieldValue Language
dc.language.isoenen_US
dc.titleAn intelligent function level backward state justification search for ATPG.en_US
dc.creatorKarunaratne, Maddumage Don Gamini.en_US
dc.contributor.authorKarunaratne, Maddumage Don Gamini.en_US
dc.date.issued1989en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractThis dissertation describes an innovative approach to the state justification portion of the sequential circuit automatic test pattern generation (ATPG) process. Given the absence of a stored fault an ATPG controller invokes some combinational circuit test generation procedure, such as the D-algorithm, to identify a circuit state (goal state) and input vectors that will sensitize a selected fault. The state justification phase then finds a transfer sequence to the goal from the present state. A forward fault propogation search can be successfully guided through state space from the present state but the forward justification search is less efficient and the failure rate is high. The backward function level search invokes inverse RTL level primitives and exploits easy movement of data vectors in structured VLSI circuits. Examples illustrated are in AHPL. This search is equally applicable to an RTL level subset of VHDL. Combinational logic units are treated as functions and the circuit states are partitioned into control states and data states. The search proceeds backwards over the control state space starting from the goal state node and data states are transformed according to the control flow. Vectorized data paths in VLSI circuits and search guiding heuristics which favor convenient inverse functions keep the number of search nodes low. Partial covers, conceptually similar to singular covers in D-algorithm, model the inverse functions of combinational logic units. The search successfully terminates when a child state node logically matches the present state and the present state values can satisfy all the constraints encountered along the search path.en_US
dc.typetexten_US
dc.typeDissertation-Reproduction (electronic)en_US
dc.subjectIntegrated circuits -- Very large scale integration -- Testingen_US
dc.subjectElectric circuits -- Testingen_US
thesis.degree.namePh.D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorHill, Fredrick J.en_US
dc.contributor.committeememberSanders, William H.en_US
dc.contributor.committeememberKuo, Sy-Yenen_US
dc.identifier.proquest9013178en_US
dc.identifier.oclc703440488en_US
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