An intelligence driven test system for detection of stuck-open faults in CMOS sequential circuits

Persistent Link:
http://hdl.handle.net/10150/184763
Title:
An intelligence driven test system for detection of stuck-open faults in CMOS sequential circuits
Author:
Sagahyroon, Assim Abdelrahman
Issue Date:
1989
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
This paper discusses an intelligence driven test system for generation of test sequences for stuck-open faults in CMOS VLSI sequential circuits. The networks in system evaluation are compiled from an RTL representation of the digital system. To excite a stuck-open fault it is only necessary that the output of the gate containing the fault take on opposite values during two successive clock periods. Excitation of the fault must therefore constrain two successive input/present-state vectors, referred to in the paper as the pregoal and goal nodes respectively. An initialization procedure is used to determine the pregoal state. Two theorems are proved establishing a 1-1 correspondence between stuck-at and stuck-open faults. As a result the D-algorithm may be used to determine the goal node. Determining the nodes was tried on many circuits and a high success rate was achieved. The pregoal is observed to have more "don't care" values. The next step is a "sensitization search" for an input sequence (X(s)) that drives the memory elements to the determined pregoal and goal states over two consecutive clock periods. It is easier for the search to reach the pregoal due to the greater number of "don't cares." Following a "propagation search" for an input sequence (X(p)) to drive the effect of the fault to an external output, the sequence of vectors (X(s)), (X(p)) will be passed to an "ALL-Fault Simulator" for verification. The simulation will be clock mode but will represent the output retention resulting from the stuck-open faults. One measure of the value of a special search procedure for stuck-open faults can be obtained by comparing the results employing this search with results obtained by searching only for the analogous stuck-at faults. A first order prediction would be a likelihood less than 0.5 that the predecessor of a stuck-at goal node would excite an opposite output in the gate containing the fault. A comparison of the two methods using the stuck-open "All-Fault Simulator" is presented.
Type:
text; Dissertation-Reproduction (electronic)
Keywords:
Integrated circuits -- Large scale integration.; Integrated circuits -- Testing.
Degree Name:
Ph.D.
Degree Level:
doctoral
Degree Program:
Electrical and Computer Engineering; Graduate College
Degree Grantor:
University of Arizona
Advisor:
Hill, Frederick J.

Full metadata record

DC FieldValue Language
dc.language.isoenen_US
dc.titleAn intelligence driven test system for detection of stuck-open faults in CMOS sequential circuitsen_US
dc.creatorSagahyroon, Assim Abdelrahmanen_US
dc.contributor.authorSagahyroon, Assim Abdelrahmanen_US
dc.date.issued1989en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractThis paper discusses an intelligence driven test system for generation of test sequences for stuck-open faults in CMOS VLSI sequential circuits. The networks in system evaluation are compiled from an RTL representation of the digital system. To excite a stuck-open fault it is only necessary that the output of the gate containing the fault take on opposite values during two successive clock periods. Excitation of the fault must therefore constrain two successive input/present-state vectors, referred to in the paper as the pregoal and goal nodes respectively. An initialization procedure is used to determine the pregoal state. Two theorems are proved establishing a 1-1 correspondence between stuck-at and stuck-open faults. As a result the D-algorithm may be used to determine the goal node. Determining the nodes was tried on many circuits and a high success rate was achieved. The pregoal is observed to have more "don't care" values. The next step is a "sensitization search" for an input sequence (X(s)) that drives the memory elements to the determined pregoal and goal states over two consecutive clock periods. It is easier for the search to reach the pregoal due to the greater number of "don't cares." Following a "propagation search" for an input sequence (X(p)) to drive the effect of the fault to an external output, the sequence of vectors (X(s)), (X(p)) will be passed to an "ALL-Fault Simulator" for verification. The simulation will be clock mode but will represent the output retention resulting from the stuck-open faults. One measure of the value of a special search procedure for stuck-open faults can be obtained by comparing the results employing this search with results obtained by searching only for the analogous stuck-at faults. A first order prediction would be a likelihood less than 0.5 that the predecessor of a stuck-at goal node would excite an opposite output in the gate containing the fault. A comparison of the two methods using the stuck-open "All-Fault Simulator" is presented.en_US
dc.typetexten_US
dc.typeDissertation-Reproduction (electronic)en_US
dc.subjectIntegrated circuits -- Large scale integration.en_US
dc.subjectIntegrated circuits -- Testing.en_US
thesis.degree.namePh.D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorHill, Frederick J.en_US
dc.identifier.proquest9000143en_US
dc.identifier.oclc703280894en_US
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